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How long does the Scatter-Gather Direct Memory Access (SG-DMA) controller's Ready signal last?
platform designer
Category: Quartus® (Qsys)
Tools: Quartus Prime / Quartus II
device:-
The grace of the ready signal on the Avalon-ST bus is parameterized, but the SG-DMA core is set to latency 0.
Therefore, the receiver of the ready signal must react by the next rising clock after the ready signal is deasserted.
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