If you check the operating waveforms of the 2-Port RAM in the device handbook, you will see that data (q) is output in one clock cycle after the read address (rdaddress) is determined. When I simulate, data is output after 2 clock cycles, which is the correct operation?

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Checking the operating waveforms of the 2-Port RAM in the device handbook, it seems that data (q) is output in one clock cycle after the read address (rdaddress) is determined. When I simulate, the data is output after 2 clock cycles.Which is the correct behavior?

simulation

Category: Specifications
Tools: Quartus® Prime
Device: Arria® 10

The differences between the operating waveforms in the handbook and the simulations are due to different RAM settings.
The operating waveforms in the handbook are waveforms when q_b port in the RAM setting "Reg/Clkens/Aclrs" tab ⇒ Output Registers is not checked.
By unchecking it, the operation will be the same as the waveform in the handbook.

https://www.altera.com/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
(Search for Mixed-Port Read-During-Write: Old Data Mode.)

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