Intel: I want to set the delay from the output register to the output pin according to the Delay from Output Register to Output Pin logic option, but the Fitter message shows Ignored Assignments. Why doesn't the constraint take effect?

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I want to set the delay from the output register to the output pin according to the Intel: Delay from Output Register to Output Pin logic option, but I get Ignored Assignments in the Fitter message. Why doesn't the constraint take effect?

Quartus Prime

Category: Timing Constraint/Analysis
Tools: Quartus® II
device:-

Incremental compilation may be involved.
If the top of the partition is Post-Fit, the previous placement result will be kept and the constraint will be ignored.
Please compile after changing Netlist Type of Top to Source File in Assingments menu ⇒ Design Partition Window.

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