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Is there a way to increase the number of AXI bus ports for the SDRAM interface between FPGA and HPS (Hard Processor System) in Cyclone V SoC?
Category: SoCs
tool:-
Device: Cyclone® V
The maximum number of ports of the SDRAM interface between FPGA and HPS of Cyclone V SoC is 3 in case of AXI.
However, it is possible to connect multiple AXI masters to one AXI slave port.
Qsys then automatically inserts an arbiter to arbitrate for the bus.
Therefore, if the AXI master on the FPGA side does not need to occupy the port (if it is allowed to share other masters), it can be accessed by multiple masters using the above method.
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