An ASMI (Active Serial Memory Interface) block is included in the design to access the configuration ROM (EPCS/EPCQ) when the FPGA is in user mode, but the ASMI dedicated pins (Data, DCLK, nCSO, ASDO) require timing. Do I need to do any constraints?

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I have an ASMI (Active Serial Memory Interface) block in my design to access the configuration ROM (EPCS/EPCQ) when the FPGA is in user mode. Do I need to do any constraints?

Category: Timing Constraint/Analysis
Tools: Quartus® II (TimeQuest)
device:-

ASMI blocks are hard blocks and do not need to be timed.

However, it is necessary to observe the "Maximum Trace Length and Loading" stated for each device family.
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cv_5v2.pdf
https://www.altera.com/en_US/pdfs/literature/hb/arria-v/av_5v2.pdf
https://www.altera.com/en_US/pdfs/literature/hb/stratix-v/stx5_core.pdf
(Search for "Trace Length and Loading".)

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