Is it okay to input an interrupt signal synchronized to a clock different from periphclk to the f2h_irq0 terminal (interrupt signal from the FPGA side to the HPS side) of the Hard Processor System (HPS)?

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Is it possible to input an interrupt signal synchronized with a different clock than periphclk to the f2h_irq0 pin (interrupt signal from FPGA side to HPS side) of Hard Processor System (HPS)?

SoC FPGAs

Category: SoCs
Tools: Quartus® II (Qsys)
device:-

Using an asynchronous interrupt signal is fine.
Even asynchronous signals are structured to be synchronized by periphclk.

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