Intel: When using Triple Speed Ethernet (TSE) IP and external PHY (RGMII), what timing constraints should be applied to the FPGA I/O?

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Intel: When using Triple Speed Ethernet (TSE) IP and an external PHY (RGMII), what timing constraints should I put on the I/O of the FPGA?

IP Timing Constraint/Analysis

Category: Timing Constraint/Analysis
Tools: Quartus® II
Device:-

Please refer to the following page for how to restrict the TSE RGMII Interface.
https://www.altera.com/support/support-resources/design-examples/intellectual-property/exm-tse-rgmii-phy.html

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