Category: Nios® II
Tools: Nios II EDS
device:-


The Nios II has a 32-bit wide address bus and a 4GB address space.
Of this 4GB, the lower 2GB is treated as cache area and the upper 2GB is treated as non-cache area.
Therefore, by setting the most significant bit to 1 for the address of the corresponding peripheral, it is possible to access the non-cache area.
In addition, dedicated macros (IORD/IOWR) are provided, and access via these macros is recommended.

For details of IORD/IOWR, refer to the following documents.
https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2sw_nii5v2.pdf
http://www.altera.co.jp/literature/hb/nios2/n2sw_nii5v2_j.pdf (Reference Japanese translation/Check the English version for the latest information)