A sample Qsys design and simulation model are provided in the Quartus II installation directory.
You can use this to simulate PCI-Express with Rootport.

The procedure is as follows.

[procedure]

1. Select the sv directory located in the Quartus II installation directory.
   
   (example)
   <install directory>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_designs/
   
   
2. Copy the .qsys file starting with pcie_de_rp_gen1_x to your working directory.
   
   
3. After starting Qsys, select File menu ⇒ Open ⇒ .qsys, then select Generate menu ⇒ Generate Testbench System, then set the following and select Generate.
   
   Create testbench Qsys system ⇒ Standard,BFMs for standard Qsys interfaces
   Create testbench simulation model ⇒ Verilog
   Allow mixed-language simulation ⇒ Turn this option off
   
   
4. Start ModelSim and move to the following directory with File menu ⇒ Change Directory.
   
   <working directory>/pcie_de_rp_gen1_x*/testbench/mentor
   　　
5. Select msim_setup.tcl from ModelSim's Tools menu ⇒ Tcl ⇒ Execute Macro.. and type ld_debug in the Transcript window to run it.
   
   
6. Right-click pcie_de_rp_gen1_x*tb from the Sim window (Sim tab) and select Add_Wave to set the waveform to observe.
   
   
7. Type run -all to start the simulation.

* You can also perform simulations with ModelSim-Altera Edition and ModelSim-Altera Starter Edition.
* This method is for v14.0. Other versions may differ slightly.