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Please let me know the release timing of various reset signals when using JESD204B IP.
IP
Category: IP
The release timing of each reset signal is as follows.
- After transceiver PHY reset (tx_ready & rx_ready are high), jesd204_tx_avs_rst_n / jesd204_rx_avs_rst_n are released synchronous to AVS clock.
- Clear txlink_rst_n / txframe_rst_n, rxlink_rst_n / rxframe_rst_n
For details, refer to the document below.
https://www.altera.com/en_US/pdfs/literature/ug/ug_jesd204b.pdf
* Search for "Reset Scheme".
Created: March 2015
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