Intel: Is there any way to interrupt access when Avalon-MM is read burst access as master?
There is no way to interrupt it, only to wait.
The Avalon specification does not specify how to interrupt Burst Read accesses.
https://www.altera.com/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf
* The timing chart and transfer procedure for Burst Read access can be viewed by searching for "pipelined read transfers with variable latency" at the above URL.
Looking at this timing chart and transfer procedure, you can see that the instruction cache is used for access when performing Burst Read according to the Avalon Specification.
And this piled-up instruction cache cannot be erased by either hard or soft means.
Therefore, when issuing a read command with burstcount, Transition cannot be completed until all read data is read.
Created: March 2015
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