We are considering compliance testing (physical layer) to ensure quality between the FPGA and PCI-Express (PCIe) edge connector. What kind of test should I perform? Also, do you have a design for that?

Narrow down by specifying conditions

There are currently 4341 results.

To ensure the quality between FPGA and PCI-Express (PCIe) edge connector, we are considering compliance test (physical layer). What kind of test should I do? Also, do you have a design for that?

PCI Express IP

Altera performs compliance testing using the design found on the Altera Wiki linked below.
http://www.alterawiki.com/wiki/PCI_SIG_Gen3_x8_Merged_Design_-_Stratix_V

Basically, we follow the contents stipulated by PSI-SIG.
The Rx side evaluation generates a loaded signal (the generator side of the BERT) and determines if it can be received correctly.
Evaluation on the Tx side causes the data received in loopback to be output from the Tx side and detected by an external error detector.

In loopback mode, it is possible to send TSOS from the HOST side and receive it to transition the Link Training Status State Machine (LTSSM).
Also, Altera Wiki has an item called Receiver Jitter Tolerance Design, so this can also be used for Rx evaluation.

Created: March 2015

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search