Analog Devices PLL: Is the timing window used for lock checking in ADF4xxx digital lock detection freely configurable?

Narrow down by specifying conditions

現在 4342 件がヒットしています。

Analog Devices PLL: Is the timing window used to check for lock freely configurable in the ADF4xxx digital lock detect?

clock & timing

For ADF41xx, ADF42xx, and ADF4001/ADF4002 synthesizers, this window is determined by the RSET value. The number of cycles counted before lock is indicated is set by the lock detect precision (LDP) bit in the R counter latch. You can choose 3 cycles or 5 cycles.
Please refer to the application note below.

AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)

(Published in November 2021)

If the problem persists

Please feel free to ask us any questions using the inquiry form.
The person in charge of Analog Devices products will answer your question.

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search

If the problem persists