Reports warnings and critical warnings as Quartus® warning messages.
The warning level is Warning < Critical Warning.

A Critical Warning is reported when there is a very real possibility that the requested action cannot be performed.
Be sure to check the cause of the problem and decide on a solution.

Possible solutions include ignoring (relaxing) this timing requirement, changing compilation options, or revising the design.


We will explain this using examples of frequently occurring Critical Warnings.

Ex) Critical Watning: Timing requirements not met.
This occurs because the timing requirements are not met for the constraints defined in the SDC file.
(This is not a problem with the FPGA design or placement and routing, so no error will be displayed.)

What users should check
1) Have you created an SDC file and registered it with Quartus®?
If you are registered, proceed to 2)
If you have not registered, this Critical Warning will occur, so please create an SDC and register it.
2) If so, are the figures in this SDC file provisional or final?
If the values are set provisionally, please review them.
If you have set it to fixed, you will need to review your compilation settings or RTL.