The following are examples of when this is necessary.
1. After configuration is complete, the input clock to the PLL is undefined.
2. When the PLL is unlocked and then re-locked, ensure that the phase relationship between the input clock and the output clock is maintained.
sea bream
⇒When the PLL locks again, the set frequency will be output, but the phase relationship is not guaranteed.
3. Using PLL_Reconfig or clock switchover in your design
 
By default, it is set to ON, meaning it uses areset.
If you wish to turn it off, please conduct thorough testing yourself before making any changes to the settings.