Yes, we do.

If you have a state machine in your design, it is possible for an asynchronous reset signal to be deasserted too close to a clock edge, causing it to go into an illegal state.

For asynchronous set/reset, the "recovery time" and "removal time" are defined near the clock edge.
This is a time that must not change for asynchronous set/reset, just like setup and hold times.
Recovery: Similar to setup time. How far before the valid clock edge.
・Removal: Similar to hold time. How long after the valid edge.

If recovery time and removal time are not taken into consideration, the timing of reset release may not be the same for each flip-flop. In this case, you will need to consider the timing of asynchronous resets or handle synchronization within the design.