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Altera: When simulating with Questa*- Altera® FPGA Edition, some ports and internal signals are not displayed.
Category: Tool
Tool: Questa* - Altera® FPGA Edition
device:-
Questa* - Altera® FPGA Edition automatically optimizes signals, which can cause some signals to be hidden.
Therefore, when you run the design load, apply the option to enable visibility to objects in the optimized design.
[Apply by GUI operation]
Apply the following option (Apply full visibility to all modules) before loading the design.
[Apply by Script Execution]
Please apply additional-voptargs=+acc option to the vsim command and run the script.
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