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DE25-Standard Development and Education Kit
Latest generation development kit featuring Altera® Agilex™ 5 SoC FPGA:
The DE25-Standard Development and Education Kitis the latest generation development kit featuring the Altera® Agilex™ 5 SoC FPGA,making it ideal for education and development of digital logic, embedded systems, robotics, and AI-related applications. In addition to a high-performance FPGA and abundant I/O functions, it also features interfaces for video output and AI processing. It also comes with a free license for Altera® Quartus® Pro Edition, allowing you to start development at no additional cost.
Supports various interfaces and AI/video processing:
To support a variety of development and educational purposes, the DE25-Standard is equipped with a wide range of general-purpose I/O interfaces, including GPIO, ADC, and HSMC, as well as a full range of basic input/output functions, including switches, LEDs, and 7-segment displays. Furthermore, it is equipped with video-related interfaces such as HDMI (1080P) output, MIPI CSI/DSI connectors, and RCA jacks, and by combining it with the AI tensor block, it can also be used for developing AI applications such as video processing and computer vision.
specification
|
Categories |
Item |
spec |
| basic information | FPGA | A5ED013BB32AE4SR1 |
| size | 166 mm x 130 mm | |
| USB-Blaster | Onboard USB-Blaster III | |
| Config Mode | Supports ASx4, 128Mbit QSPI Flash | |
| cooling | Optional active heat sink | |
| FPGA side | DDR4 | 1GB (32-bit bus, no ECC, shared with HPS) |
| SDRAM | 64MB (32-bit bus, no ECC) | |
| Video Output | HDMI 1.4 (supports 1080P), composite video input | |
| Camera/Display | 1 x 2-lane MIPI connector | |
| audio | 24-bit audio codec (MIC-In, Line-In, Line-Out) | |
| analog input | 8-channel ADC (2x5 headers) | |
| Other I/O | IR TX/RX, 3.3V 2x20 DE-GPIO, HSMC (4 transceivers) | |
| User I/O | 10 LEDs, 4 buttons, 10 slide switches, 6 7-segment switches | |
| sensor | Temperature sensors, fan controllers | |
| HPS side | DDR4 | 1GB (32-bit bus, no ECC, shared with FPGA) |
| storage | MicroSD Socket | |
| communication | Gigabit Ethernet + RJ45 | |
| USB | USB host x 2 (Type-A), UART to USB | |
| display | 128x64 LCD | |
| sensor | Accelerometer | |
| User I/O | 1x LED, 1x Button, Cold Reset Button, 3.3V 1x6 GPIO | |
| software | Development environment | FPGA sample code, Linux BSP |
| license | Includes a free Altera® Quartus® Pro Edition license |
Block Diagram
Layout
Contents
01 DE25-Standard Board
02 Type-C USB Cable
03 AC Power Cord
04 12V 60W Power Supply
05 Quick Start Guide
06 Four Silicon Footstands
07 Fan (Installed)
Others
Note: The information on this page is based on information available as of the date of creation (August 2025), but we cannot guarantee its accuracy or completeness.