What is PCIe?

PCI Express (PCIe) is a high-speed serial interface standard for connecting CPUs to various devices (GPUs, storage, network equipment, etc.).

With PCIe, communication speeds have improved dramatically with each generation, increasing significantly from 2.5 GT/s in Gen1 to 32 GT/s in Gen5, and currently up to Gen7.

PCIe enables high-speed and efficient data transmission.

And in order to support such high-speed communication, the quality of the "clock" is an extremely important factor in PCIe systems.

Why a PCIe reference clock is needed

In PCIe systems, the reference clock (Refclk) serves as the timing reference for data communication.

Since transmitting and receiving devices use this clock as a reference to send and receive data at precise timing, the quality of the clock affects the stability of communication.

Using an inappropriate clock can cause data errors and link training failures. (For example, linking up with PCIe Gen3 when PCIe Gen4 is expected.)

In particular, with the recent increase in speed (Gen4/Gen5 and later), the required jitter (RMS jitter) performance of the clock has increased.

The PCIe specification uses a 100 MHz reference clock as a basis and specifies frequency accuracy of approximately ±300 ppm and high jitter requirements.

While it is possible to generate the above-mentioned clocks using FPGAs or PLLs within CPUs, these are often insufficient to meet PCIe standards, requiring a PCIe-compliant clock product. *Gen4 and later versions have particularly stringent clock requirements (jitter requirements).

*The diagram is an excerpt from application note AN946: PCI-Express 4.0 Jitter Requirements provided by Skyworks.

Furthermore, the PCIe clock architecture shown in the diagram above is an example of how PCIe clocks are actually used.

Common Clock

• Independent clocks (SRNS/SRIS)

SRIS, in particular, is gaining increasing adoption as an important method from the perspective of cable connectivity and expandability.

In PCIe systems, multiple clock architectures (common clock and independent clock) may coexist within a single system to ensure compatibility with external connections such as add-on cards.

Thus, the PCIe clock is not merely a frequency source, but a crucial component that determines the overall performance and reliability of the system.

What is HCSL?

HCSL stands for High-Speed Current Steering Logic, and it is a high-speed differential clock signal format mainly used in PCIe.

There are two types of HCSL: current-driven and push-pull. The current-driven type is called standard HCSL, while the push-pull type is called Low-Power HCSL (LP-HCSL).

The following are termination circuits for HCSL and LP-HCSL.

In the push-pull type diagram, it is assumed that a 100Ω termination resistor is built into the transmitting side.

In current-driven circuits, a termination resistor is required, as shown in the diagram.

On the other hand, with a push-pull type connector, an external termination resistor is not required.

In recent years, PCIe clock devices are increasingly adopting LP-HCSL, which is internally similar to a push-pull type, in order to improve power consumption and ease of installation.

(Push-pull type clock devices may have a built-in 100Ω or 85Ω termination resistor on the transmitting side.)

Skyworks PCIe Clock Product Lineup

The following is a list of Skyworks' clock generator product lineup.

In recent years, the demand for high-precision clock quality has been increasing in data centers, telecommunications infrastructure, broadcasting equipment, industrial equipment, and other applications.
Furthermore, in AI and data center applications, massive amounts of data are transferred between GPUs and accelerators, so the performance of the PCIe interface is crucial to the overall processing power of the system.

Consequently, PCIe clock speeds also require high PCIe Gen requirements, as well as devices that comply with the standards but have a performance margin.

In response to these challenges, Skyworks boasts industry-leading low jitter performance and provides clock solutions tailored to various PCIe applications.

PCIe-dedicated clock generator

Si5332

The Si5332 is a clock generator specifically designed for general-purpose clock generation, in addition to PCIe applications. It supports PCIe Gen1 through Gen6.

The output clock count is available in 6ch, 8ch, and 12ch configurations.

In addition to HCSL output for PCIe, it also supports output in LVPECL/LVDS/LVCMOS formats.

Therefore, the Si5332 can be used to integrate clock sources for PCIe applications and other purposes, which is expected to reduce the number of components.

Furthermore, the Si5332 is also available in a version with a built-in crystal oscillator, eliminating the need for an external crystal oscillator and reducing the time required for matching tests.

Summary

With the increasing speed of PCIe, clock products are required to have high performance (frequency accuracy/jitter performance) and flexibility.

With Skyworks products

- Low jitter performance with a margin over the specifications

・Supports clock architectures such as Common/SRIS

Our lineup offers a reduced number of components, solutions to address increasing system complexity, and PCIe compliance plus additional features, allowing for optimal selection based on your application.

In particular, the Si5332, as a highly flexible general-purpose clock, can realize configurations like the one shown in the diagram below.

By selecting the appropriate devices according to design requirements, it is possible to maximize the performance and reliability of PCIe systems.

If you're unsure about what PCIe system configuration to use or which PCIe clock to choose, please feel free to contact us.