Download reference design materials for Skyworks clock products and Intel FPGA from here
What is the importance of reference designs/clocks in FPGA peripheral design?
After selecting the FPGA, while proceeding with the design of peripheral parts such as clocks,
"It's listed in the reference design, but we have to use a cheaper device because of cost considerations..."
As a result of proceeding with the selection independently, do you have the following experience?
・ The jitter performance (e.g. phase noise) required by the FPGA was not met
・An unexpected malfunction occurred.
・The clock product was reconsidered/changed to solve the problem, resulting in extra costs/man-hours for board revision.
These problems can be solved by selecting low-jitter products in the selection of components around the clock,
Risk can be reduced by adopting a reference design whose operation has been confirmed.
Skyworks clock products use proprietary Digital PLL and fractional divider technology to achieve a level of low jitter performance not found in other companies.
The low jitter is the main factor, and we have entered into reference design agreements with many FPGA/SoC vendors, including Intel.
In this article, we will use Intel, which has the most abundant reference designs, as an example.
The Skyworks clock products installed in each development kit are listed, including the clock tree.
Please use it as reference information when selecting clock products.
Skyworks Reference Design Partnership
Skyworks clock products have low jitter, flexible frequency customization, and support for various clock formats.
Due to its high performance, it is compatible with control devices such as FPGA, SoC, and CPU, and can be used safely as a peripheral device.
Since it can maximize the performance of FPGA, etc., it has been widely adopted and has been concluded as a reference design.
This reliability is a great advantage for FPGA designers, leading to a reduction in component selection and verification man-hours.
Intel Reference Design List
Many Skyworks clock products are installed in Intel FPGA development kits as reference designs.
Specifically, as shown in the slide below, for a wide range of product series from the latest and most high-end Intel Agilex® to relatively low-end Cyclone®,
Four timing product groups from Skyworks (crystal oscillator, clock generator, clock buffer, jitter attenuator) are installed.
Introducing the Intel FPGA Development Kit
Intel Agilex® I-Series FPGA Development Kit
The figure below is a block diagram of the evaluation board of the Intel Agilex® I-Series FPGA development kit and the Skyworks clock product that it is equipped with.
〇 This development kit supports the following.
・PCIe Gen 5.0
・Compute Express Link(CXL)v1.1
・400G Ethernet connectivity
〇High-Speed interface
・R-Tile:PCIe 5.0x16,edge fingers &MCIO
・F-Tile:2x QSFPDD, 2x 28/56G
〇 As a Skyworks clock product
・Si5391 (clock generator)
・Si52204 (PCIe clock generator)
・Three points of Si510 (crystal oscillator) are installed.
Among them, the Si5391 is a clock generator with excellent low jitter.
What clocks are on other FPGA development kits?
The Intel Agilex® I-Series FPGA development kit mentioned above is just an example, and it is installed in many other Intel Corporation FPGA development kits (20 or more).
Therefore, in addition to Intel Agilex®, such as Stratix® 10 DX,
Information on the model numbers and clock trees (block diagrams) of all clock products that are installed are summarized in one document.
If you would like to request materials, please apply from [Download materials here] below.
*These information are estimated by Skyworks based on each manufacturer's information at the time of acquisition. Please judge the applicability after evaluation by the customer.
* Information subject to change without notice. the Company do not make any guarantees regarding the accuracy of the information.
About Skyworks clock products
Jitter performance of Si5391
As mentioned above, Skyworks' clock products have the strength of low jitter.
Si5391 has a track record of being installed in Intel Agilex® FPGA,
It boasts the lowest jitter among Skyworks clock generators.
The figure on the right shows the phase noise measurement results of the Si5391.
The vertical axis represents phase noise and the horizontal axis represents offset frequency.
The phase noise component at each offset frequency is expressed as [dBc/Hz] in the figure,
RMS Jitter is obtained by integrating the phase noise in the range of 12kHz to 20MHz.
Its value will be 65 fs RMS.
(*Measurement conditions are 3.3V LVPECL 156.25MHz output, BW: 12kHz to 20MHz)
Click here for the Si5391 datasheet.
Jitter performance of Si5341
The Si5341 is hard pin compatible with the Si5391.
It will be the device of the previous generation, but the jitter performance is not inferior
It is installed in many Intel evaluation boards.
It is a proven device with many inquiries even now triggered by FPGA.
The figure on the right shows the phase noise measurement results of the Si5341.
(*Measurement conditions are 2.5V LVDS 625MHz output, BW: 12kHz to 20MHz)
Click here for the Si5341 datasheet.
Skyworks clock product list
Below is a list of Skyworks clock products.
The horizontal axis shows, from left to right, the crystal oscillator, clock generator, jitter attenuator (jitter cleaner), and buffer.
The vertical axis is jitter performance. The higher you go, the better the jitter performance, and the lower you go, the cheaper the product.
At the right end, we also handle products that conform to time synchronization and PCIe standards.
Inquiry/Quotation
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