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High transfer rate performance and low cost for smart connected systems *1

Cyclone 10

​Intel​ ​Cyclone 10 family offers cost and power savings over previous generation Cyclone FPGAs.
Cyclone 10 GX FPGAs offer high bandwidth performance with 10.3G transceiver capability, 1.4Gbps LVDS, and up to 72-bit wide 1,866Mbps DDR3 interface.
Cyclone 10 LP devices offer low static power and cost-optimized features.

  • Cyclone 10 GX FPGAs are optimized for high-bandwidth, high-performance applications such as industrial vision, robotics, and automotive infotainment.
  • Cyclone 10 LP FPGAs are optimized for low static power, low cost applications such as I/O expansion, sensor fusion, motor/motion control, chip-to-chip bridging, and control.

Both the Cyclone 10 GX and LP families support vertical migration, allowing you to start your design in one device and later move to a more suitable density device when the design is finalized.

Cyclone 10 GX Device Family List

product line 10CX085 10CX105 10CX150 10CX220
Number of LEs (K) 85 104 150 220
Number of memory blocks (20K) 291 382 475 587
Memory block (Kbit) 5,820 7,640 9,500 11,740
Distributed memory (Kbit) 653 799 1,152 1,690
Number of hardened single-precision floating-point multipliers/adders 84 125 156 192
Number of global clock networks 32 32 32 32
Regional Clock Count 8 8 8 8
18 x 19 bit multiplier count 168 250 312 384
Number of hard memory controllers (DDR3/L, LPDDR3) 1 2 2 2
Maximum number of LVDS channels (1.434Gbps) 72 118 118 118
Maximum User I/O Pins 192 284 284 284
Up to 3V I/Os 48 48 48 48
Number of transceivers (10.3Gbps) 4 12 12 12
Number of PCI Express ® (PCIe ®) Hard IP Blocks
(up to Gen2 x4)		 1 1 1 1

Cyclone 10 LP Device Family List

product line 10CL006 10CL010 10CL016 10CL025 10CL040 10CL055 10CL080 10CL120
Number of LEs (K) 6 10 16 25 40 55 80 120
Number of memory blocks (9K) 30 46 56 66 126 260 305 432
memory block
(K bits)		 270 414 504 594 1,134 2,340 2,745 3,888
18x18 bit
number of multipliers		 15 23 56 66 126 156 244 288
phase lock
Number of loops (PLL)		 2 2 4 4 4 4 4 4
Number of global clock networks 10 10 20 20 20 20 20 20
Number of LVDS channels 65 65 137 124 124 132 178 230

Cyclone 10 GX FPGAs

Double the performance, at least half the cost *1

Intel Cyclone 10 GX FPGAs are the first low-cost devices on the 20nm high-performance process, helping boost performance in cost-sensitive applications.

  • Industry's First Low-Cost FPGA Supporting 10.3Gbps Transceiver I/O
  • 1,866Mbps high performance external memory interface
  • 1.434Gbps LVDS I/O
  • Industry's first low-cost FPGA with IEEE 754 compliant hard floating-point DSP block

application

Cyclone 10 GX FPGAs are ideal for a wide range of applications that demand higher levels of core and I/O performance as the need for scalable accelerated processing increases system demands.
Examples of typical end markets are:

  • Automotive infotainment
  • smart vision camera
  • industrial robot
  • machine vision
  • Industrial programmable logic controller (PLC)
  • Professional AV system

Improved productivity and integration technology, faster time to market

  • Combining 20nm devices with an advanced design environment to achieve state-of-the-art compile times for low-cost FPGAs
  • Standard support for advanced features such as Partial Reconfiguration and SEU (Detection and Correction)
  • Faster compile times for faster design iterations and timing closure
  • C-based design entry using the Intel FPGA SDK for OpenCL ™, providing an FPGA-friendly design environment
  • System-level design environment with Qsys system integration tools
  • DSP Builder for Intel FPGA - model-based DSP environment in the MATLAB/Simulink ® environment
  • Small Footprint, High Performance, Low System Power, High Reliability and Efficiency, and Short Time-to-Market with Intel Enpirion ® PowerSoC Solutions Strengthen Support for Cyclone 10 FPGAs

OpenCL and the OpenCL logo are trademarks of Apple Inc. used with permission by Khronos.

Cyclone 10 LP FPGAs

Cut costs and power consumption in half *1

The Intel Cyclone 10 LP FPGA family builds on the low-cost, low-power features of the Cyclone FPGA series. Ideal for high-volume, cost-sensitive functions, Cyclone 10 LP FPGAs are designed for a wide variety of general-purpose logic applications.

Reduced power consumption

Built on a power-optimized 60nm process, Cyclone 10 LP FPGAs build on the low-power features of the previous generation Cyclone V FPGAs. The latest generation devices reduce core static power consumption by up to 50% compared to previous generations.

Reduced system cost

All Cyclone 10 LP FPGAs require only two core power supplies to operate, simplifying power distribution networks and reducing board cost, board space, and design time. The flexibility of Cyclone 10 LP FPGAs allows you to design with smaller, lower-cost devices while reducing your total system cost.

application

Cyclone 10 LP FPGAs are ideal for cost-sensitive applications that demand lower static power consumption while the need for scalable acceleration demands more system interfaces.
Examples of typical end markets are:

  • I/O expansion
  • interface
  • Bridging
  • sensor fusion
  • industrial motor control

 

*1 Compared to the previous generation Cyclone FPGA, price comparison is based on list price.
A test measures the performance of a component in a specific test on a specific system.
Due to differences in hardware, software, system configuration, etc., actual performance may differ from performance tests and evaluations posted.
We recommend that prospective purchasers consult other sources of information to evaluate overall performance.
For more information on performance and benchmark results, please visit http://www.intel.com/benchmarks/.