Arria V FPGA: Achieving a Balance of Cost, Performance, and Power Consumption

^Arria® V FPGAs offer the optimal balance of performance, cost, and power consumption required for midrange applications such as remote wireless units, 10G/40G line cards, and video studio mixers. High-speed FPGA fabric, high-speed I/O, and high-speed data-rate transceivers deliver high system performance while meeting the cost and power consumption requirements of these applications.

Arria V Family Types

The Arria V family includes the following four products:

FPGA

Arria V GX FPGA (with built-in 6.375 Gbps transceiver)
Arria V GT FPGA (with built-in 10.3125 Gbps transceiver)

SoC FPGAs

Arria V SX SoC FPGA (ARM-based HPS and integrated 6.375 Gbps transceiver)
Arria V ST SoC FPGA (ARM-based HPS and integrated 10.3125 Gbps transceiver)

SoC FPGA – Customizable ARM processor-based SoC

SoC FPGAs reduce system power consumption, system cost, and board space by integrating a hard processor system (HPS), consisting of a processor, peripherals, and memory controller, with an FPGA fabric via a high-bandwidth interconnect backbone. The combination of HPS and Altera's 28nm low-power FPGA fabric delivers the flexibility and rich DSP blocks of an application-class ARM® processor ecosystem and performance of Arria V FPGAs.

Industry leading low power consumption

The Arria V device family is manufactured using TSMC's 28nm Low-Power (28LP) process, delivering a balance of cost, performance, and industry-leading low power consumption.

Hard memory controller
PCI Express Gen2 x4 hard IP block with multi-function support
Variable precision digital signal processing (DSP) block optimized for FIR filters
HPS (SoC FPGAs only)

Dual ARM Cortex™-A9 MPCore™ processors

・Embedded Peripherals (Ethernet, USB, Flash, etc.)

• High-bandwidth HPS/FPGA interconnect exceeding 125 Gbps

These hard IP blocks, which provide ready-to-use functions, allow for the use of more logic resources to develop differentiating features compared to soft logic. Furthermore, Arria V FPGAs offer the most comprehensive design protection of any FPGA, including features such as 256-bit AES with volatile and non-volatile keys to protect valuable IP assets.

With its hard IP functions and features including an integrated 10.3125 Gbps transceiver, the Arria V FPGA is ideal for meeting the performance and ever-evolving standards requirements of mid-range applications in end markets such as wireless, broadcast equipment, and video.

complete solution

Arria V FPGAs offer soft IP cores, design guidelines, and documentation to help simplify your designs in various markets.

Overview of the Arria V GX FPGA Family