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HIGH-SPEED SENSOR INTERFACE SOLUTIONS

​Simplifying the development of receiver and control for the latest endoscope sensor, IMX742.

We offer a one-stop solution for high-speed reception and protocol conversion of the cutting-edge IMX742. This significantly reduces the time and effort required for complex circuit design and register initialization.

Technical consultation and inquiries

Resolving protocol inconsistencies & automating sensor initial setup sequences

Why Macnica

Why Macnica is the choice for high-speed sensor interfaces

01 / FPGA EXPERTISE

Advanced FPGA design technology

We provide comprehensive support for high-speed interface implementation and timing convergence.

02 / SENSOR KNOWLEDGE

Familiarity with major sensors

We have a thorough understanding of the electrical characteristics and initial setup sequences of various sensors, and we propose the optimal connection configuration.

Solution Overview

Overall picture of the receiving solution

This resolves protocol inconsistencies between sensors and the host SoC, providing an optimal architecture.

INPUT

image sensor

SONY IMX742
High resolution / High frame rate

SLVS-EC

MACNICA SOLUTION

RECEIVE & BRIDGE

Receiving and control solutions

Bridge Chip (dedicated LSI)

FPGA IP (IP Core)

MIPI CSI-2 / User-Designed Interface

OUTPUT

Host system

Processor / Post-processing
SoC / CPU / GPU / DSP

Proprietary image processing and AI analysis

The link to the target sensor is here.​

BRIDGE Chip OVERVIEW

What can a Bridge Chip do?

Sensor and host SoC are directly connected on a single chip.

  • Compact and low-power: Minimizes board area and BOM cost.
  • Automatic sequence control: Fully automated startup and register initialization upon power-on.
  • Minimizing host load: Offloading reception and conversion processing reduces processor load.

BRIDGE Chip Internal Architecture Overview

High-speed Rx PHY / Protocol receiver SLVS-EC
Intelligent control engine (Ready-made) Auto Seq / Calib
Tx output interface MIPI CSI-2

Bridge Chip Intelligence

Six intelligent functions enabled by Bridge Chip​

Package complex sensor control, eliminating additional development costs.

01Automatic Calibration

Automatic Calibration

Automatically corrects lane skew to maximize the receive margin for high-speed transmission.

02Gain Setting

Gain control

With simple settings from the host, parameters are reflected in the internal registers all at once.

03Exposure Time Control

Exposure time control

It can be set intuitively without having to be aware of the sensor's specific drive sequence.

04Shutter Mode Control

Shutter control

Smooth and secure switching between global and rolling modes.

05Trigger & Mode Control

Trigger and shooting control

It synchronizes with external trigger signals with high precision, ensuring reliable shooting timing.

06LED Strobe Control

LED strobe control

It outputs a light emission pulse that is perfectly synchronized with the sensor's exposure timing.

FPGA Internal Block Diagram Example

[ IP ] SLVS-EC Rx Core

▼ AXI-Stream / FIFO

[User Area] Image Processing Pipeline / ISP / Proprietary AI

*Encrypted RTL, sample design, and simulation model are provided as a package.

FPGA IP

High-reliability receiver IP core to be integrated into our FPGAs

Compatible with major FPGAs. Directly connects to proprietary image processing logic.

  • Multi-vendor support: Supports major FPGA families.
  • Direct connection to existing pipelines: Seamless data transfer to proprietary ISPs and image processing circuits.
  • Focus on core technologies: IP-based physical layer and receive control, and concentrated on developing differentiated algorithms.

Evaluation Environment

Start real-world testing early using the evaluation environment.

Image evaluation can be performed as quickly as possible without waiting for the actual circuit board to be completed.

HARDWARE

Kit contents

Bridge/FPGA board + connection interface.

SOFTWARE

Verification GUI

It includes tools for register settings and image preview, allowing for immediate image verification from a PC.

VALUE

Benefits

Early operational verification

Solution Selection

Three delivery options to choose from, tailored to your development phase and product requirements.

If it's only for dedicated LSI connection, then Bridge Chip Reduces BOM costs, minimizes board area and power consumption, and allows for implementation with zero initial development effort. inquiry If you want to incorporate unique IP core features, use FPGA IP. Supports proprietary image processing and integrated multi-sensor input on a single chip, enabling flexible reuse of FPGA assets. inquiry Evaluation Environment: Evaluation Platform - Short-term verification and feasibility testing; Pre-production image verification before actual device design; Actual device verification of signal quality; Risk elimination during specification development phase. Recommended: Sensor selection initial stage / Verification inquiries.

Are you having trouble configuring a high-speed sensor interface?

Go to the inquiry form