Overview

V-by-One® HS Tx/Rx IP is an IP for realizing V-by-One HS high-speed interface.
V-by-One® HS is a next-generation high-speed interface standard proposed by THine Electronics for imaging and video equipment.
By implementing Mpression's V-by-One® HS Tx/Rx IP in Intel® FPGA, the number of signals can be reduced compared to conventional LVDS interfaces, leading to significant reductions in product costs.

Features

• Achieves a maximum transmission bandwidth of 4 Gbps per lane (depending on the FPGA used)
• Supports not only video formats regulated by VESA/SMPTE, etc., but also user-customized video formats
• Flexible multi-lane design is possible according to customer's transmission band
• Equipped with a self-check function (FieldBET function) for checking communication between sending and receiving IPs

specification

corresponding device

• Altera® Agilex™ 5E (Group B)
• Altera® Agilex™ 7(F Tile)
• Altera® Stratix® 10 GX (H/L Tile)
• Altera® Arria® 10 GX
• Altera® Cyclone® 10 GX

*Please contact us for information regarding the Altera Stratix® V GX, Arria® V GX, and Cyclone® V GX families.

Offerings

• Cryptographic RTL (Verilog HDL)
• Reference design
• Simulation environment (for Modelsim)
• User's Manual
• Reference Design User's Guide

Logic Resources (Altera® Arria® 10 GX)

Diagram

Evaluation Board

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