NXP i.MX 6/7 DDR Design Guidelines

As memory interfaces become faster, there is a growing demand for stricter board designs, and memory-related operational problems are also on the rise.

We have prepared DDR design guidelines that show the design flow and debug flow, and aim to prevent defects by performing design using appropriate steps, and to quickly resolve problems by implementing the mechanisms necessary for debugging. Did.

Follow guidelines to shorten design time and prevent defects from entering the market, and bring defect-free products to market in the shortest possible time.

This is a design guideline document that summarizes the points to check when designing DDR for NXP i.MX 6 / i.MX 7. Please refer to it when designing DDR.

table of contents

1.First of all

2. DDR design flow

3. DDR debug flow

4. Appendix 

　4-1. DDR Register Programming Aid 

　4-2. DDR Stress Test 

4-3. Items to check in board simulation results

4-4. i.MX 6/7 series and compatible DRAM

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1. This material is not for sale. Resale or reproduction without permission is prohibited.
2. This document is subject to change without notice.
3. We have taken every possible measure to create this document, but if you notice any questions, errors, or omissions, please let us know.
4. Please note that we cannot be held responsible for the effects of operating the circuits, technologies, and programs covered in this document.
5. This document is supplementary material when using the product. When using the product, please also use the English version of the documentation.

i.MX 6/7 Series DDR Tool from NXP

Please check the information on the NXP website carefully before designing DDR for i.MX 6/7.

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