Supported SERDES protocols

AVANT Platform supports the SERDES in the table below.

(Excluding AVANT-E)

Low power consumption/Low heat generation

・16nm Low Power Fin-FET process optimized for low power consumption

・Significantly lower power consumption per operating frequency (up to 2.5 times lower power consumption than devices of the same scale and operating frequency)

EBR (internal memory)

AVANT-E is equipped with a large capacity memory (EBR) of up to 35.6Mb (36kbit x 990blocks).

It is also possible to configure line buffers, frame buffers, etc. with one FPGA chip without using external memory.

Also, the external memory I/F supports LPDDR4, DDR4, and DDR5.

Other components

Miniaturization: Significant miniaturization is possible with FPGAs of the same class

・11×9mm for 262kSLC

・15×13mm for 637kSLC

Programmable I/O

・Compatible with various I/F including differential and 3.3V such as SGMII, MIPI, LVDS, subLVDS, LVCMOS33

・Instant-on support: 637kSLC devices can be fully configured in 60ms

・3.3V IO support, 1.8Gbps/lane MIPI D-PHY, 1.6Gbps/lane LVDS

DSP block

・Up to 1800 18×18 Multipliers

・One 18x18 Multiplier can be split into four 8x8 Multipliers (up to 7200 installed)

Security

・Post Quantum

・AES256-GCM,ECC & RSA

・User data encryption

Package lineup