[CrossLink-NX] Parallel to MIPI CSI-2 / DSI Display Interface Bridge

Parallel to MIPI CSI-2 / DSI Display Interface Bridge reference design for CrossLink-NX.

Features are as follows.

・Compliant with MIPI D-PHY v1.2, MIPI DSI v1.2, and MIPI CSI-2 v1.2 Specifications

・Supports MIPI DSI and MIPI CSI-2 interfacing up to 6 Gb/s for Soft D-PHY and up to 10 Gb/s for Hard D-PHY

・Supports 1, 2, or 4 MIPI D-PHY data lanes

・Supports non-burst mode with sync events for transmission of DSI packets only

・Supports low-power (LP) mode during vertical and horizontal blanking

・Supports common MIPI DSI compatible video formats (RGB888, RGB666)

For details, please visit the official Lattice website by clicking the button below. (Always use the latest version of the reference design.)

[CrossLink-NX] MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge reference design for CrossLink-NX.

Features are as follows.

・Single CSI-2 input (RGB888, RAW8, RAW10, or RAW12) to single or dual channel RGB888 LVDS outputs (RGB888)

・Single DSI input (RGB888 or RGB666) to single or dual channel LVDS output (RGB888 or RGB666)

・Supports MIPI DSI input up to 1.5Gbps per lane

・Supports OpenLDI at 1.2Gbps per lane

・Compliant with CSI-2 Specification v1.1

・Compliant with DSI Specification v1.1

For more information, please click the button below to go to the Lattice official website. (Please always use the latest version of the reference design.)

* Macnica also has a Japanese manual, so if you would like a Japanese manual, please click the button below.

[CrossLink-NX] 1 to N MIPI CSI-2/DSI Duplicator

1 to N MIPI CSI-2/DSI Duplicator reference design for CrossLink-NX.

Features are as follows.

・One RX channel is duplicated to one or two TX channels (RX / TX channel can have one, two, or four lanes)

・For RX, Hard IP enables 1.5 Gbps per lane and saves FPGA resources. Soft IP performance is 1.2 Gbps per lane.

・Hard IP is used on TX channel(s), enabling 1.5 Gbps per lane performance

・Non-continuous clock mode on RX channels is possible provided the continuous clock can be obtained internally or fed directly from the pin.

・Maximum 1.5 Gbps Tx per lane (10 Gbps maximum bandwidth)

For details, please visit the official Lattice website by clicking the button below. (Always use the latest version of the reference design.)

[CrossLink-NX] 4 to 1 Image Aggregation

This is a 4 to 1 Image Aggregation reference design for CrossLink-NX.

Features are as follows.

・CSI-2 4 lanes x 4 channel inputs at 371 Mbps/lane inputs

・Camera sensors are configured by CrossLink^-NX using I2C interface

・RAW10 data are converted to RGB888 on all channels

・Output image can be changed by the on-board switch

For details, please visit the official Lattice website by clicking the button below. (Always use the latest version of the reference design.)

[CertusPro-NX] SLVS-EC to MIPI CSI-2

SLVS-EC to MIPI CSI-2 reference design for CertusPro-NX.

Features are as follows.

・Compliant with MIPI D-PHY v1.2, and MIPI CSI-2 v1.2 Specifications

・Supports MIPI CSI-2 interfacing up to 5 Gb/s for SLVS-EC and 6 Gb/s for Soft TX D-PHY

・Supports 1, 2, 4, 6 or 8 RX data lanes

・Supports 1, 2, or 4 MIPI TX D-PHY data lanes

・Supports low-power (LP) mode during vertical and horizontal blanking

For details, please visit the official Lattice website by clicking the button below. (Always use the latest version of the reference design.)

[Certus Pro-NX] SubLVDS to MIPI CSI-2 Image Sensor Bridge

SubLVDS to MIPI CSI-2 Image Sensor Bridge reference design for CertusPro-NX.

Features are as follows.

・Supports 4-, 6-, 8-, or 10-lane SubLVDS input to 1-, 2-, or 4-lane MIPI CSI-2 output

・Supports input lane bandwidth of up to 1.25 Gbps and output lane bandwidth of up to 1.5 Gbps

・Image cropping option

・VSYNC and HSYNC can be generated to control sensor timing

・Dynamic parameter setting through I2C

For details, please visit the official Lattice website by clicking the button below. (Always use the latest version of the reference design.)

[CertusPro-NX] MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge reference design for CertusPro-NX.

Features are as follows.

・Single CSI-2 input (RGB888, RAW8, RAW10, RAW12 or RAW14) to single or dual channel RGB888 LVDS outputs (RGB888)

・RX channel can have one, two, or four lanes with the bandwidth up to 1.5 Gbps per lane using RX D-PHY Soft IP

・Number of TX data lanes is four (RGB888) per TX channel

・Maximum TX bandwidth is 945 Mbps per lane

・Image cropping option is available in case of CSI-2 input

For details, please visit the official Lattice website by clicking the button below. (Always use the latest version of the reference design.)

[Certus Pro-NX] N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation reference design for CertusPro-NX.

Features are as follows.

・Two to eight Soft RX channels can be aggregated

・All RX channels must be in the same configuration

・Maximum RX bandwidth is 1.5 Gbps per lane

・Maximum TX bandwidth is 2.5 Gbps per lane

・Number of TX lanes can be one, two, or four

For details, please visit the official Lattice website by clicking the button below. (Please always use the latest version of RD.)