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This is a page of FPGA reference designs created by Macnica that are often requested by customers.
MIPI reference designs (excluding DSI to FPD-Link) can be downloaded for free by entering your information.
[What you can get]
・Reference design project file set
・Simple manual materials*
* Please use after acknowledging the disclaimer described in the manual.
For SERDES/other reference designs, simple manuals can be downloaded without registration. If you need a reference design, please contact us from inquiry.
We will update the lineup from time to time, so please take advantage of it.
MIPI reference design
In addition to MIPI CSI-2 and DSI Rx/Tx, this reference design can convert LVDS ↔ MIPI DSI, which is in high demand for interface conversion such as LCD. If you apply from each download button, you can get the design immediately, so you can try MIPI's interface bridge without spending man-hours.
MIPI DSI Transmitter/Receiver
MIPI CSI-2 Transmitter/Receiver
RAW10 to MIPI CSI-2 and MIPI CSI-2 to RAW10 designs. A 720p (pixclk=74.25MHz) bridge is assumed. Please apply from the download button below.
LVDS to MIPI DSI
It is a design that separates Full-HD into odd/even pixels (pixclk=74.25MHz), receives the sent LVDS (FPD-Link) x 2ch, combines them and sends them with MIPI DSI.The LVDS format is equivalent to FPD-Link.Please apply from the DL button below.
MIPI DSI to LVDS
Full-HD (pixclk=148.5MHz) design sent by MIPI DSI is divided into odd pixels and even pixels and transmitted by 7:1 LVDS ((Data 4Lane + Clock 1Lane) x 2ch) at 74.25 x 7 = 519.75Mbps. Design.The LVDS format is equivalent to FPD-Link.Please apply from the DL button below.
MIPI DSI to FPD-Link
Similar to MIPI DSI to LVDS, the Full-HD (pixclk=148.5MHz) design sent by MIPI DSI is divided into odd and even pixels, 74.25 x 7 = 519.75Mbps 7:1 LVDS ((Data 4Lane + Clock 1Lane ) x 2ch), but the FPD-Link Tx IP is used, and there is a restriction up to Data 8Lane due to the specifications of that IP.
If you would like this reference design, please contact us using the inquiry form below and let us know that you would like the "MIPI DSI to FPD-Link" reference design. We will send you the design by email.
SERDES reference design
If you would like any of the reference designs listed below, please contact us using the inquiry form at the bottom of the page. We will send you the design by email.
PRBS7 Loopback
This design is a Serdes loopback reference design for CertusPro-NX using PRBS Generator/Checker. The PRBS7 data is output from the PRBS Generator built into the PMA Controller in the Serdes block, looped back, and bit errors are detected using the built-in PRBS Checker.
The design includes an LMMI (Lattice Memory Mapped Interface) certified module to enable the PRBS Generator/Checker.
8B10B 4Byte Mode Loopback
This design is a Serdes loopback reference design for CertusPro-NX using the Generic 8B10B protocol. Generate 32bit data with a simple data generator, output in Generic 8B10B 4Byte Mode and loop back.
8B10B 1Byte Mode Loopback
This design is a Serdes loopback reference design for CertusPro-NX using the Generic 8B10B protocol. Generate 8bit data with a simple data generator, output in Generic 8B10B 1Byte Mode and loop back.
Other reference designs
If you would like any of the reference designs listed below, please contact us using the inquiry form at the bottom of the page. We will send you the design by email.
GDDRX4, GDDRX5 loopback
This design is a loopback reference design using the 8:1, 10:1 serialization/deserialization logic GDDRX4 (8:1) and GDDRX5 (10:1) installed in the I/O part of CrossLink-NX. . It can be used as a real-phase sample of GDDRX4 and GDDRX5.
Odd/Even Pixel Separation/Split
Single design with odd/even pixel separation/splitting.
color bar generator
This is a design for a single color bar generator.
SED/SEC
This is a reference design that realizes the function of Soft Error Detection/Collection.
Reference design from Lattice
A reference design from Lattice is also available. Please refer to the link button below.
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