Ⅰ-1. Power monitoring and power sequence control

・Contributes to the reduction of the board area by integrating the power supply monitoring mechanism with a discrete circuit into an IC.

・It has 6 to 12 channels of multi-power monitoring ports, 368 trip point settings, and high-precision monitoring in units of 15 to 20 mv.

・It is possible to detect power supply anomalies and their signs, and record the details for use in failure analysis.

Ⅰ-2. IO Expansion/Level Shift

・Compact, low-power, low-cost FPGA solves ASIC and CPU port shortages

・Adjust the voltage level between ICs that do not match the voltage level

・At Lattice, it can be realized collectively with a 1-chip type FPGA with built-in Flash that can be driven by a single 3.3V power supply.

Ⅰ-3. Secure boot with a small FPGA equipped with a security engine as hardware

Realize the following functions required by NIST 800-193 with a small FPGA

・Protection: Sign configuration data

・Detection: XO3D verifies the signature

・Recovery: After verification, start booting from another flash if there is a problem

↓↓↓Details can be downloaded from the bottom of the page↓↓↓

Ⅱ-1. Multi-axis synchronous control of Stepping Mmotor

High precision control of multiple axes with 1 chip by outputting PWM by taking advantage of the parallel processing capability of FPGA 

II-2. Servo motor FOC control

・Accuracy can be improved by leaving the current loop calculation from the MCU to the FPGA

・Provide libraries such as Park conversion and Clarke conversion

・Integration of encoder I/F and filter circuits can be implemented together

・Lattice can realize these processes in a minimum 10mm square package.

Ⅱ-3. Head board control and ADC

・Simultaneously control multiple head boards while suppressing heat generation with a small, low power consumption FPGA

・Monitor analog signal of temperature sensor with built-in ADC

Ⅱ-4. Communication between multiple substrates such as ink/laser substrates

・Flexible response to requests such as terminal board expansion with low cost and small FPGA

・It is possible to incorporate functions such as logic IC integration and IO expansion as an aid to the MCU on the board.

・Ether-connect reference design available from Lattice

Ⅱ-5. Reducing wiring for inter-board communication cables

・Wiring is reduced by eliminating the LVDS Clock Lane and performing communication.

・Skew between Data/Clock does not occur

↓↓↓Details can be downloaded from the bottom of the page↓↓↓

III-1. Summary of Sensor IF

・Integrate multiple channels of I2C, UART, and GPIO and send and receive with a single wire

・Up to 7 channels can be combined (total data rate is 7.5 Mbps or less)

・I2C supports 100Kbps, 400Kbps [Fast-Mode], 1Mbps [Fast-Mode Plus]

- GPIO can transmit and receive up to 16bit and 2Mbps per channel

III-2. Summary of Channel Link

・Channel Link output from CCD and CIS image sensors via AFE can be received by a small, low-power FPGA.

・Hard macro enables 1:7 Deserialization with 1 chip

↓↓↓Details can be downloaded from the bottom of the page↓↓↓

Ⅳ-1. Summary of Video IF

・Display IF (FPD Link and MIPI DSI) conversion and transmission to the main board with SerDes (PCIe and eDP)

・Lattice can be realized with a minimum 10x10mm FPGA

Ⅳ-2. Summary of Wifi Module IF

CPU load can be reduced by using a small, low-power FPGA to control PCIe and process data on the CPU.

↓↓↓Details can be downloaded from the bottom of the page↓↓↓

V-1. Summary of Logic ICs

Collectively control multiple Sensor IFs used in FAX and card readers

・It is possible to perform gesture detection, voice recognition, and human detection by AI processing with a small FPGA.

・Realized by overwhelmingly low power consumption AI solution by Lattice FPGA