Hard Processor System side SDRAM ModelSim simulation method

Narrow down by specifying conditions

現在1888件がヒットしています。check

Design FPGA/CPLD/ASIC Intel

Hard Processor System side SDRAM ModelSim simulation method

This document describes how to use ModelSim to simulate the HPS Hard Memory Controller implemented on the Hard Processor System (HPS) side of an Altera SoC FPGA device.

Here, ModelSim-Altera is used, but ModelSim-SE etc. can also be used for simulation.

"ModelSim Simulation Method for Hard Processor System SDRAM"

Document overview

Quartus II v14.0

ModelSim - Altera 10.1e

1.First of all

2. Simulation procedure

2-1. Hardware creation and testbench generation in Qsys

2-2. Creating files required for simulation

2-3. From starting ModelSim-Altera to running a simulation

3. Details

3-1.test_program.sv

3-2.top.sv

3-3.load_sim.tcl

Hard Processor System side SDRAM ModelSim simulation method

Document overview

Related Documents