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SoC FPGA Hard Processor System Addressing Methods v14.0
This document describes the relationship between the address map of the Hard Processor System (HPS) of Altera SoC FPGA devices and the address space of Qsys.
SoC FPGA Hard Processor System Addressing Methods v14.0
Document overview
<Contents>
1.First of all
2. Interface between HPS and FPGA
3. HPS address map
3-1. JPS address space
3-2. MPU view
3-3. Non-MPU view
3-4. Qsys Design Example
3-5. Slave address on Qsys seen by HPS
3-6. Slave address on HPS seen from FPGA
3-7. L3 Interconnect Address Remap Register
4. References
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