Sample collection of bare metal applications using HWLib v16.0

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Design FPGA/CPLD/ASIC Intel

Collection of samples of bare metal applications using HWLib v16.0

This document describes the configuration and sample code of HWLib for Intel® SoC FPGA.

The content is useful for designers who develop software using the provided HWLib.

Quartus® Prime v16.0

Intel® SoC FPGA Embedded Design Suite (EDS) v16.0

1. Configuration of HWLibs

2. Coverage of HWLib API

3. Samples supplied with SoC EDS (bare metal)

4. On-site sample (bare metal)

5. HWLib samples provided by Altima

- GPIOs

- Global Timer

-Clock Manager

-FPGA Manager

- Watchdog Timer

- General Purpose Timer

-Cache Management

- Interrupt Controller[SGI]

- DMA Controller

-MMUs

- Measure time using Global Timer

- ECC (On-Chip RAM)

- DMA x ACP

6. Introduction of sample code public site