Ultrasonic diagnostic equipment (signal/image processing)

Narrow down by specifying conditions

現在2149件がヒットしています。check

Product Pickup FPGA/CPLD/ASIC Intel® Programmable Solutions Group (now Altera Corporation)

Signal processing solutions

Signal processing is performed by FPGA or DSP. Calculations that require fast processing are performed on the FPGA, while slower calculations can be performed on the DSP.
Explain why FPGAs are faster than DSPs.

Signal processing differences between DSP and FPGA

Sequential processing of the DSP is shown in Figure 2. As shown, one adder circuit is reused, so the number of clocks is required for each tap.
With FPGAs, parallel processing can be performed on several hundred taps at once with one clock, and dividing the circuit increases the number of clocks, but it is also possible to reduce the circuit area according to the division.

In this way, FPGAs can flexibly adjust speed and area (cost) as needed.
In addition, recent FPGAs support "partial reconfiguration," which allows the circuit configuration to be rewritten while other parts are operating, so it is no longer necessary to increase the circuit scale each time functions are added.

Variable precision DSP block

Variable precision DSP block is a DSP block built in FPGA that can configure multipliers of various sizes with one DSP block built in FPGA.

Conventional DSP blocks used one DSP block for 9x9bit, and two DSP blocks for 27x27bit or 18x36bit, so DSP blocks could not be used efficiently.
The newly supported "variable precision DSP block" can configure up to three 9x9bit DSP blocks, 27x27bit and 18x36bit DSP blocks in one DSP block. ^Intel® is the only FPGA that supports "Variable Precision DSP Blocks" that allow DSP blocks to be used efficiently in this way.

table 1. Accuracy available in Arria® V and Cyclone® V

Multiplier that can be configured in one DSP block		Multiplier that can consist of two DSP blocks
multiplier mode	quantity	multiplier mode	quantity
9x9	3	18X18 complex multiplier	1
12X12	2	36X36 * complex multiplier	1
16X16	2	Multiplier configurable with 4 DSP blocks
18X19	2	18X25 * complex multiplier	1
18X25	1	18X36 * complex multiplier	1
27X27	1	27X27 complex multiplier	1
18X36*	1	54X54 * complex multiplier	1

*Additional logic required outside DSP block

Enabling High Performance DSP Applications with Arria V or Cyclone V Variable Precision DSP Blocks (PDF)

Webinar: Variable-Precision Stratix V DSP Architecture for Precision, High-Performance Signal Processing

floating point arithmetic

Intel has developed algorithms for optimally designing circuits that perform floating-point processing.

MathWorks' Simulink ^® If you add the DSP design tool "DSP Builder" as an option to the"Intel DSP Builder Standard Blockset”and supports floating point"Intel DSP Builder Advanced Blockset”It adds two libraries called . Since each function is organized in these libraries, efficient and high-performance arithmetic circuits can be configured.

Instead of building a datapath consisting of basic floating-point operators, for example multiply, add, and square sequentially, the floating-point compiler consolidates the basic operators into a single function or datapath. You can generate a fused datapath with

Variable-Precision DSP Architecture for Precision, High-Performance Signal Processing (PDF)

Implementation of floating-point DSP using FPGA

List of filter IPs

Please refer to the following for filter IP that can be used with FPGA. Click here for details

Image processing solutions

Since FPGAs are often used for image processing, IPs for image processing are abundantly provided. Functions that do not affect differentiation or standard functions can use these IPs to focus their design resources on core technology development for differentiation.

In addition, by using an FPGA with a built-in processor, image generation and high-load processing can be performed by the FPGA, and other functions can be processed by software. Compared to having a processor outside the FPGA, the interface between the hardware and software is an order of magnitude faster, and since it is inside the FPGA, it has a large number of signal lines, so algorithm processing can be finely divided. Board cost can also be reduced because there is no need for board wiring between the FPGA and the processor.

Video/Image Processing (VIP) Suite

The video/image processing (VIP) suite provided by Intel is an IP group that collects Intel's image processing related IP and provides it at a low price.

IPs range from simple color space conversions to complex video scaling functions that implement programmable polyphase scaling.

Shorten Video Design Design Period with FPGA and IP Core

Optimizing video processing applications with design examples

adaptive scaler

This is an IP capable of image scaling processing of Full High-Definition (D5 standard) class pixel rate.
Various algorithms such as Gaussian, Nearest Neighbor, Bi-Linear, and Bi-Cubic can be dynamically set as pixel interpolation.

This IP was developed by an affiliated company of Macnica, so we provide smooth support together with FPGA.

ベイヤー変換(ACPI)

Bayer pattern conversion IP that converts Bayer pattern format data (RAW data) to RGB color data.
ACPI (Adaptive Color Plane Interpolation) algorithm is used to convert Bayer pattern format data (RAW data), which is generally used as the output format for single-chip CCDs, to RGB color data.

This IP was developed by a Macnica affiliate, so we can provide smooth support together with FPGAs.

JPEG XR

JPEG XR is a compression format for still images that is an improvement of "Windows Media Photo" developed by Microsoft.
Compared to JPEG2000, the circuit scale is about half and the amount of memory used is a fraction, so high-speed compression is possible.
It does lossless compression to avoid compression noise and supports resolutions up to 32bit.
Microsoft did not support JPEG2000, but since JPEG XR was developed by Microsoft, Windows Vista and later operating systems support it as standard.

H.264

H.264 is a widely used compression technology for video.
Playback processing is light and algorithmic differences are unlikely to occur, so it can be processed by a CPU, but compression processing is heavy and algorithmic differences are likely to occur, so we recommend using an FPGA.

Site Search