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The Intel® SoC Embedded Design Suite (EDS) provides the following development tools that enable you to develop firmware and application software on the Intel SoC hardware platform.
Development tools provided by Intel SoC EDS
 Hardware/software hand-off tools |
| Linux application development |
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| Bare metal application development |
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| FPGA Adaptive Debug |
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| design example |
Industry's First FPGA Adaptive Software Toolkit: ARM Development Studio 5 (DS-5) Altera Edition
The ARM DS-5 Altera Edition Toolkit is provided under an exclusive agreement with Intel as part of the Intel SoC Embedded Design Suite (EDS).
Combining the system development-ready ARM DS-5 tool suite with Intel SoC devices, this toolkit gives embedded developers an unparalleled level of visibility and control across the chip.
Features of the DS-5 Altera Edition
| USB-Blaster alone connects to software and hardware debugging environments |
| Automatically generate register views for FPGA peripherals |
| CPU software instructions associated with application events and FPGA hardware events |
| Non-intrusive tracing |
| Hardware cross-trigger between CPU and FPGA |
| Simultaneous debug and trace of Cortex-A9 cores and CoreSight™ enabled IP cores synthesized on FPGA |
| Streamline ready: analysis of software load and bus traffic across CPU and FPGA |
| Industry's most advanced multi-core debugger for ARM |
| JTAG-based system-level debugging, gdbserver-based debugging in one package |
| Yocto plugin for Linux-based application development |
| Analysis and debugging functions for integrated OS |
Hardware/software handoff
Intel's hardware/software interface utilities enable hardware and software teams to work independently and use their own familiar design flows.
These utilities generate interface files for software design flows from Quartus® II output files. A utility program generates a device tree.
A device tree is an industry standard way of describing hardware to an operating system (primarily Linux).
Specify the hardware corresponding to the board and FPGA configuration so that the corresponding driver is loaded when the kernel is launched.
