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Product PickupFPGA/CPLD/ASIC Intel

The SoC FPGA has a hard memory controller.
This memory controller supports ECC (Error Correction Code) on both HPS (Hard Processor System) and FPGA side.

Due to the increase in soft error rates, many designers are starting to consider adding error correction code (ECC) to external DDR memories.
ECC can be used to correct single-bit errors, greatly reducing the possibility of system failure.

Intel® SoC FPGAs are the perfect devices to support ECC.
By integrating all the necessary logic functions, ECC for external memory can be achieved simply by increasing the width of the DDR memory.

 

HPS Multiport Memory Controller Features

Features

  • Supports DDR2, DDR3, Mobile DDR, and LPDDR2
  • Speeds from 400 MHz to 533 MHz (800 to 1066 Mbps)
  • x8, x16, or x32 interface with ECC
  • x8 and x16 components with two chip selects

high performance

  • Low latency full rate operation
  • Deficiency Aging Round Robin (DRR) Arbitration
  • Prioritization and weighting per port/burst
  • Priority bypass for latency-sensitive traffic
  • High efficiency with command/data reordering

low cost

  • Hard logic in HPS (HPS dedicated I/O)
  • Share up to 6 ports with FPGA fabric

Features of FPGA Multiport Memory Controller

Similarities with HPS hard memory controller

  • Equivalent device support
  • equivalent performance
  • Equivalent behavior

Differences from the HPS hard memory controller

  • Not directly connected to HPS
  • Up to 3 hard memory controllers in FPGA
  • PHY enabled by soft logic (bypass)
  • I/O can be used by soft logic (bypassed)

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