Overview of Arria V FPGA Family - Semiconductor Business -Macnica

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The 28nm Arria ® V FPGA family offers the right balance of performance and low cost/power consumption for mid-range applications such as remote radio units, 10G/40G line cards, and video studio mixers.

Table 1. Arria V GT/GX FPGA Family Overview (1)

function	5AGX A1	5AGX A3	5AGX A5	5AGX A7	5AGX B1	5AGX B3	5AGX B5	5AGX B7
Equivalent logic element (LE) count	75,000	149,430	190,000	242,950	300,000	362,730	420,000	503,500
Adaptive Logic Module (ALM)	28,302	56,389	71,698	91,679	113,208	136,879	158,491	190,000
Number of M10K memory blocks	800	1,039	1,180	1,366	1,510	1,726	2,054	2,378
M10K Memory (Kb)	8,000	10,390	11,800	13,660	15,100	17,260	20,540	23,780
memory logic array Block (MLAB) (Kb)	463	892	1,173	1,448	1,852	1,961	2,532	2,943
18x19 bit multiplier number	480	792	1,200	1,600	1,840	2,090	2,184	2,278
Variable precision DSP block	240	396	600	800	920	1,045	1,092	1,139
Maximum number of transceivers (6.375 Gbps / 10.3125 Gbps)	12/0	12/0	24/0	24/0	24/0	24/0	36 / 0	36 / 0
PCI Express® (PCIe®) Number of hard IP blocks	1	1	2	2	2	2	2	2
Maximum User I/O Pins	480	480	544	544	704	704	668	668

Table 2. Arria V GX FPGA Package Summary and User I/O (LVDS, Transceiver) (2)

device	5AGXA1	5AGXA3	5AGXA5	5AGXA7	5AGXB1	5AGXB3	5AGXB5	5AGXB7	5AGTD3	5AGTD5
F672 (27mm)	336, 9	336, 9	288, 9	288, 9	-	-	-	-	-	-
F896 (31 mm)	480, 12	480, 12	384, 18	384, 18	384, 18	384, 18	-	-	322, 12, 2	-
F1152 (35mm)	-	-	544, 24	544, 24	544, 24	544, 24	528, 24	528, 24	544, 12, 4	528, 12, 4
F1517 (40 mm)	-	-	-	384, 18	704, 24	704, 24	668, 36	668, 36	704, 12, 4	688, 12, 8

note:

1. Arria V GX devices are offered in -4, -5, and -6 speed grades.
2. Pin migration within each package is possible.

Table 3. Arria V GT FPGA Family Overview (1)

function	5AGTD3	5AGTD5
Equivalent logic element (LE) count	362,730	503,500
Adaptive Logic Module (ALM)	136,879	190,000
Number of M10K memory blocks	1,726	2,378
M10K Memory (Kb)	17,260	23,780
Memory Logic Array Block (MLAB) (Kb)	1,961	2,943
18x19 bit multiplier number	2,090	2,278
Variable precision DSP block	1,045	1,139
Maximum number of transceivers (6.375Gbps / 10.3125Gbps)	12/4	12/8
Number of PCIe hard IP blocks	1	1
Maximum User I/O Pins	704	688

Table 4. Arria V GT FPGA Package Summary and User I/O (LVDS, Transceiver) (2)

device	5AGTD3	5AGTD5
F672 (27mm)	-	-
F896 (31 mm)	322, 12, 2	-
F1152 (35mm)	544, 12, 4	528, 12, 4
F1517 (40 mm)	704, 12, 4	688, 12, 8

note:

1. Arria V GT devices are offered in -5 speed grade.
2. Pin migration within each package is possible.

Table 5. Industrial Temperature Range Support

device	package	speed grade
Arria V GT	F896, F1152, F1517	I5
Arria V-GX	F672, F896, F1152, F1517	I5

Table 6. Arria V SX SoC FPGA Family Overview

function	5ASXB3	5ASXB5
Equivalent logic element (LE) count	350,000	462,000
Adaptive Logic Module (ALM)	132,075	174,340
Number of M10K memory blocks	1,729	2,282
M10K Memory (Kb)	17,288	22,820
Memory Logic Array Block (MLAB) (Kb)	2,014	2,658
18x19 bit multiplier number	1,618	2,186
Variable precision DSP block	809	1,068
Maximum number of transceivers (6.375 Gbps / 10.3125 Gbps)	30/0	30/0
Number of PCIe hard IP blocks	2	2
Maximum User I/O Pins	528	528
Maximum Hard Processor System (HPS) I/Os	216	216
FPGA hard memory controller	1	1
HPS hard memory controller	3	3
Processor core (ARM ® Cortex™-A9)	dual	dual

Table 7. Arria V SX SoC FPGA Package Summary and User I/O (LVDS, Transceiver)

device/ package (mm x mm)	F896			F1152			F1517
	1.0 mm 31x31			1.0mm 35x35			1.0mm 40x40
	Number of FPGA I/Os	Number of HPS I/Os	Maximum number of transceivers (6.375Gbps / 10.3125Gbps)	Number of FPGA I/Os	Number of HPS I/Os	Maximum number of transceivers (6.375Gbps / 10.3125Gbps)	Number of FPGA I/Os	Number of HPS I/Os	Maximum number of transceivers (6.375Gbps / 10.3125Gbps)
5ASXB3	170	216	12/0	350	216	18/0	528	216	30/0
5ASXB5	170	216	12/0	350	216	18/0	528	216	30/0

Table 8. Arria V ST SoC FPGA Family Overview

function	5ASTD3	5ASTD5
Equivalent logic element (LE) count	350,000	462,000
Adaptive Logic Module (ALM)	132,075	174,340
Number of M10K memory blocks	1,729	2,282
M10K Memory (Kb)	17,288	22,820
Memory Logic Array Block (MLAB) (Kb)	2,014	2,658
18x19 bit multiplier number	1,618	2,136
Variable precision DSP block	809	1,068
Maximum number of transceivers (6.375 Gbps / 10.3125 Gbps)	30/6	30/6
Number of PCIe hard IP blocks	2	2
Maximum User I/O Pins	528	528
Maximum Hard Processor System (HPS) I/Os	216	216
FPGA hard memory controller	1	1
HPS hard memory controller	3	3
Processor core (ARM Cortex-A9)	dual	dual

Table 9. Arria V ST SoC FPGA Package Summary and User I/O (LVDS, Transceiver)

device/ package (mm x mm)	F896			F1152			F1517
	1.0 mm 31x31			1.0mm 35x35			1.0mm 40x40
	Number of FPGA I/Os	Number of HPS I/Os	Maximum number of transceivers (6.375Gbps / 10.3125Gbps)	Number of FPGA I/Os	Number of HPS I/Os	Maximum number of transceivers (6.375Gbps / 10.3125Gbps)	Number of FPGA I/Os	Number of HPS I/Os	Maximum number of transceivers (6.375Gbps / 10.3125Gbps)
5ASTD3	170	216	6/2	350	216	12/2	528	216	12/6
5ASTD5	170	216	6/2	350	216	12/2	528	216	12/6

・ Arria V Device Family Overview (English / PDF)
- Variable precision DSP block architecture in Arria V and Cyclone ® V FPGAs

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