CvP stands for Configuration via Protocol, a method of configuring an FPGA over a PCI Express* ( PCIe* ) link.

​^CvP is supported in ^Intel®​ ​^Agilex​ ​^™, ^Intel® Stratix® 10 ^Intel® Cyclone® 10 GX, ^Intel® Arria® 10, ^Arria® V, ^Cyclone® V, and ^Stratix® V device families.

In the CvP configuration scheme, separate images (configuration data) are created for peripheral logic and core logic.

・System cost is reduced by reducing the capacity of ROM ^* placed on the same PCB as FPGA

*Flash device that stores configuration data for FPGA

• No need to reprogram the flash ^** to update the FPGA.

**A flash device placed on the same PCB as the FPGA to store the FPGA's configuration data.

・No need to power down the system to update the FPGA core fabric

No need to reboot the host or reinitialize the FPGA full chip to update the FPGA core fabric

・The load of the application can be changed by updating the design quickly.

・Configuration from ROM placed on the same PCB as FPGA
- Simple circuit configuration
- Configuration is basically performed when powering on the FPGA
- Updating the FPGA core fabric requires flash rewriting, and requires circuitry for flash rewriting

・Configuration in CvP
- The circuit configuration connects FPGA and PCIe, and arranges flash for peripheral configuration
- Peripheral part configuration is performed when the FPGA is powered on, and FPGA core fabric configuration is performed at an arbitrary timing from the PCIe host.
- FPGA core fabric updates can be done via PCIe from a PCIe host