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Design FPGA/CPLD/ASIC Intel® Programmable Solutions Group (now Altera Corporation)

hello.

My name is Intel F. Hanako and I provide technical support for Intel® FPGA products at Macnica.

 

Even if you create a register in a logic circuit, it may be merged and removed by optimization when compiling with Quartus ® Prime.

This is the result of the Quartus Prime compiler aggressively minimizing resources while reducing wasted resources, so it 's basically a good thing.

 

★ How to check the deleted or merged register information due to compiler optimization?

　 See "How to check deleted or merged register information" on this page.

 

However, depending on the user, there may be situations or reasons for wanting to keep the registers that were deleted by optimization.

For example... (see here)

 

The previous method showed how to take advantage of Quartus Prime's logic options.

I would like to show you how to embed these options as attributes directly in your HDL code.

Which options apply?

The logic options used here are:

 

Disable Register Merging Option /　Preserve Registers Option /Preserve Fan-out Free Register Node Option

 

And the point of distinguishing between these is whether the signal of the register finally affects (outputs) the output pin of the device.

If the signal in the register is to the output pin of the device...

option name used to hold the register

(Assignment Name)
Influenced (output)

Disable Register Merging

or Preserve Registers
Not affected (no output)

Preserve Fan-out Free Register Node

How to write attributes

As an example, let the name of the register to be retained be my_reg.

Disable Register Merging Option

VHDL

signal my_reg : std_logic; attribute dont_merge : boolean; attribute dont_merge of my_reg : signal is true;

Verilog HDL

reg my_reg /* synthesis dont_merge */;

Verilog-2001 / System Verilog

(* dont_merge *) reg my_reg;

Preserve Registers option

VHDL

signal my_reg : std_logic; attribute preserve : boolean; attribute preserve of my_reg : signal is true;

Verilog HDL*1

reg my_reg /* synthesis preserve = 1 */;

Verilog-2001*1

(* preserve = 1 *) reg my_reg;

Notes (1)

・ “= 1” after preserve can be omitted.

・ Preserve can be replaced with syn_preserve, which is applied by synthesis tools of other manufacturers. (compatible)

Preserve Fan-out Free Register Node option

VHDL

signal my_reg: std_logic; attribute noprune: boolean; attribute noprune of my_reg: signal is true;

Verilog HDL*2

reg my_reg /* synthesis noprune = 1 */;

Verilog-2001 / System Verilog*2

(* noprune *) reg my_reg;

Notes (2)

・ “= 1” after syn_noprune can be omitted.

- syn_noprune can be replaced with syn_noprune used by synthesis tools of other manufacturers. (compatible)

 

 

The above is a method to retain registers that have been deleted during compilation.

Please use it as needed.

 

Please refer to this page for how to set logic options using Quartus Prime's Assignment Editor instead of embedding options directly in the HDL code.

 

 

Reference: Quartus Prime Online Help

・ Disable Register Merging Option

・ Preserve Registers option

・ Preserve Fan-out Free Register Node option

Click here for recommended articles/materials

How to retain registers deleted by compilation (logic option edition)

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