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Hi, I'm Shiwashiwa.
This time, I will explain how to select an FPGA, which is necessary before generating a memory IP.
In the previous article "Memory IP ~ Accurate and Efficient Data Transfer ~", I wrote about the configuration of the memory IP, which is the circuit that controls the DDR memory.
I thought, "I know the configuration of the memory IP, so let's generate the memory IP!"
Launch the IP Catalog where you can select the memory IP you want to generate from Quartus® Prime Tools.
When I try to select which memory IP to generate,
Wrinkled: "Oh, it seems that there were types of memory IP other than DDR2, DDR3, and LPDDR2..."
Therefore, this time it is about the selection of FPGA that must be done before memory IP generation.
FPGA selection
To generate a memory IP, I need to know which FPGA family supports which memory.
This is where a tool called the EMIF Spec Estimator comes into play.
EMIF Spec Estimator is a tool that can select FPGA according to memory specifications.
By using this, you can know the performance of the memory interface of each device.
* The EMIF Spec Estimator is explained in detail in a previous article.
Also, as a result of investigating whether there is a list that immediately shows which FPGA supports which memory,
When clicking and opening "Device Support" from the page of External Memory Interface on Altera's homepage, there was a table of External Memory Interface Support Device Memory Type.
The table below shows the FPGA family on the vertical axis and the memory type on the horizontal axis.
(*Specifications may have changed for the latest devices, so please check the Altera website.)
Also, the numbers in the table are the memory type's maximum operating frequency and maximum data transfer rate for each FPGA family.
Since the maximum operating frequency is determined for each FPGA family and memory type,
Even with the same memory, different devices have different maximum operating frequencies.
For example, for DDR3 memory, Stratix® V has a maximum operating frequency of 933 MHz, whereas
The maximum operating frequency for Stratix® 10 is 1066 MHz.
This time the Cyclone® V was chosen for my project.
Looking at the item of Cyclone® V, RLDRAM and QDR are not supported,
I found that it supports LPDDR2, DDR2, and DDR3.
In this article, I found out how to select FPGA which FPGA supports which memory
Next time, I would like to write about how to generate memory IP.
Summary
- FPGA selection methods include EMIF Spec Estimator and External Memory Interface Support Device Memory Type
- EMIF Spec Estimator is useful for detailed searches such as I/O standards, clock rates, interface types, etc.
- If you want to know at a glance the maximum operating frequency of each device and which device supports which memory, check External Memory Interface Support Device Memory Type
wrinkle wrinkle memory series
・ 『SDR and DDR ~Processing DDR data with FPGA~』
We have summarized the processing of DDR data by FPGA.
・ 『Memory IP ~Accurate and Efficient Data Transfer~』
Summary of memory IP building blocks and overview
・ 『Memory IP - Selection of FPGA -』
Summarized how to select which FPGA supports which memory
・ 『Memory IP ~Generation and Parameter Input~』
Summarized how to generate memory IP and presets that can easily set parameters
・ 『Memory IP - Saving and Recalling Presets -』
Summarized points to note when using memory IP presets and how to save and recall presets