11th Cases of Malfunctions Caused by Patterns in FPGA Power Supply Design and Solutions

Part 11 introduces "Examples of malfunctions caused by patterns in FPGA power supply design and solutions".

As you know, various problems can occur when designing power supplies.

 
This time, we will focus on cases caused by patterns. This problem is particularly likely to occur in products with a switching frequency of 1MHz or higher. We hope that you will find the examples of malfunctions introduced below and their solutions useful in your future FPGA power supply designs.

Case 1: Using an electrolytic capacitor for the input capacitor

  • Symptoms: Severe fever.
  • Cause: The input capacitor supplies switching current, so a high di/dt square wave current flows through it. In the case of large current output, the allowable RMS ripple current of the electrolytic capacitor will be exceeded, causing abnormal heat generation and affecting reliability.
  • Countermeasure: Place a low ESR capacitor such as a ceramic capacitor as the input capacitor close to the device.
  • Note: Capacitors with higher ESR will have higher ripple. Use capacitors with low ESR.

Case 2: Using an electrolytic capacitor for the output capacitor

  • Symptom: Large output voltage ripple and severe heat generation.
  • Cause: Electrolytic capacitors have high ESR, so the output ripple voltage increases. Large ripple noise causes malfunction of the circuit connected to the load.
  • Countermeasure: Place a low ESR capacitor such as a ceramic capacitor as the output capacitor close to the device.
  • Note: Capacitors with higher ESR will have higher ripple. Use capacitors with low ESR.

Case 3: Temperature characteristics and DC bias characteristics of ceramic capacitors

  • Symptom: Output voltage drops as temperature increases. or unstable.
  • Cause: If the actual capacitance value under the usage conditions is not taken into account, a sufficient filter effect cannot be obtained, causing abnormal operation of the power supply circuit.
  • Countermeasures: Take into consideration the decrease in capacity due to temperature, or use a capacitor with good temperature characteristics.
  • Note: When selecting a capacitor, take into account the increase or decrease in capacitance due to temperature characteristics.

Case 4: Back side arrangement of output capacitor COUT

  • Symptom: Output voltage is not stable. I have a severe fever.
  • Cause: COUT is placed on the BOTTOM layer via VIA.
  • Countermeasure: Connect high switching current loops such as power MOSFET, input, and output capacitors on the same layer of the TOP layer as short as possible.
  • Note: Strictly adhere to connection patterns on the same layer where high switching current loops occur.

Case 6: Stretching the VFB (feedback pin) node

  • Symptom: Noise other than the switching frequency appears on the output voltage.
  • Cause: The line to the VFB terminal after voltage division was long, and the signal line was adjacent and affected.
  • Countermeasure: Shorten the wiring pattern to the VFB pin. Also keep signal lines away.
  • Note: Keep wiring traces short for high impedance nodes such as VFB nodes.

Case 6: Location of analog power supply decoupling capacitance

  • Symptom: Unstable operation. Fever.
  • Cause: The analog power input terminal closest to the device is the power supply VIA, and there is a capacitance outside of it, so decoupling is not working.
  • Countermeasure: Place the device, capacitor, and VIA of the power supply source so that analog power input decoupling is performed in the vicinity of the device.
  • Note: Place parts carefully in order to ensure decoupling and filter function.

Case 7: Incorrect input filter constant

  • Symptom: Device not working.
  • Cause: Depending on the device, the recommended circuit is to connect an RC filter with a resistance of 1.0 to 20Ω and a capacitance of 1.0uF to the VIN input. If you make a mistake in the resistance value and connect 1kΩ, a voltage drop will occur due to the bias current of the VIN pin. By reducing the input voltage, VIN UVLO is detected and operation stops.
  • Countermeasure: Change the resistance value to the recommended value.
  • Note: Check the constants of the components used in the circuit.

 

I believe that by knowing the above examples, you will be able to proceed with future designs without stress.

 

Well, next time is finally the last time. I would like to introduce the 12th "Summary of the FPGA power supply design process" of FPGA, which I have introduced over 11 times since January.


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