Introduction

Hello. It's Tott.

When I saw the title of this column, I thought, "Huh? ’ you might think.

Actually, there was a continuation to this column series, "The Difference Between Synchronous and Asynchronous Circuits."

* If you haven't read the series "Differences between Synchronous and Asynchronous Circuits," we recommend starting with "Differences between Synchronous and Asynchronous Circuits - Comparison Edition." *

synopsis

After I finished writing the previous column, I told my seniors that I understood that FPGAs should be designed using synchronous circuits.

Me: "Sixteen. 』

Senpai: ``How many LEs do you think would be consumed if it was a 17-bit counter? 』

Me: "Because LE consists of 4-input 1-output LUT and 1 register... 17 pieces? 』

Senpai: "30 points! Create a 17-bit counter in both schematic and language.”

So I made a 17 bit counter and checked it.

Just like last time, I made a 17-bit synchronous counter in the schematic and checked the compilation report.

Me: "Huh? It consumes 23 LE... 』

 

When I wondered why, the answer was in my words earlier.

 

With synchronous counters, as the number of bits increases, the number of input ports of the AND element increases, so one LUT cannot compensate for one counter.

 

* Regarding LUT, see Ume Onigiri's "What is an FPGA?" ] Please refer to.

 

Therefore, it consumes 23 LEs of Cyclone ® IV E.

I made a 17 bit counter in my language and checked the compilation report

A 17-bit synchronous counter in the language consumed 17 LEs.

 

Why? ? I wondered,

 

I compared the two Resource Property Editors.

Schematic 17-bit Synchronous Counter Compared to Language 17-bit Synchronous Counter

 

Comparing the LE internals of the 17-bit synchronous counter in the schematic and the 17-bit synchronous counter in the language

 

・The 17-bit synchronous counter in the circuit diagram does not use a carry chain.

・The carry chain is used for the language's 17-bit synchronous counter.

 

* Carry Chain is dedicated wiring that connects adjacent LEs to realize high-speed operations such as counters and adders *

* Conditions under which Carry Chain is used: 1. Counter design in language 2. Design using Altera megafunction LPM counter *

 

It turns out that the language's 17-bit synchronous counter uses a carry chain, so it doesn't consume extra LEs.

 

Also, in FPGA design, LE consumption can be reduced by using the carry chain of the LE architecture, so I understood that synchronous circuit design is suitable.

Summary of this time

・There is a carry chain in the LE architecture.

・In FPGA synchronous circuit design, LE consumption can be reduced.

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