Hello. It's the chief.

This time, as the second installment of the "Rookie's Plunge into New Areas" series, I will introduce useful information on tool specifications, starting with the "Bimyo relationship" between technology that performs complex processing and FPGAs.

One day, I got a call from a customer saying, "I have a question about Quartus® II."

The newcomer said, "Tools, Quartus II~♪", and said, "Yes, that's a question about Quartus II. I'd like to hear from you."

"What criteria does Quartus II use to decide whether to use DSP blocks or internal logic during logic synthesis?" 』

It's soooooooooooooooooooooooooooooooooooooooooooooooo ! A voice echoed in the chief's head.

Quartus II Criteria? What should I do...

After I told him that I would get back to him and hung up the phone, I started researching "the bimyo relationship between DSP and FPGA".

DSP is an abbreviation of Digital Signal Processor (Digital Signal Processor) or Digital Signal Processing (Digital Signal Processing), but the DSP Block in Altera's FPGA is digital signal processing that performs arithmetic operations on digital signals. was. In this column, we will use the expression DSP for digital signal processing.

DSPs are primarily used in a variety of applications such as video surveillance systems, broadcast equipment, wireless base stations, medical imaging, and radar.

DSP blocks containing multipliers and adders are prepared as hard IP in Altera FPGAs so that arithmetic processing can be executed quickly and efficiently.

For more information on Altera FPGA DSP solutions, see "Technology" → "DSP" at the top of the Altera website.

Then you can browse new features, IP, reference designs, materials, etc. in the latest devices.

アルテラ社 FPGA に DSP を実装するには、

1. Using DSP Blocks

2. Use internal logic

There are two methods.

By the way, this DSP block and internal logic are named differently depending on the device family.

*However, the latest Cyclone V is called DSP block/ALM like Arria V and Stratix V.

And there are three ways to do a design that includes DSP:

1. Assemble your design using Altera-provided IP

2. Build your own HDL description base

3. Create a calculation model using Altera's DSP Builder library in the environment of MathWorks' software "MATLAB® / Simulink®" and convert it to HDL

In the case of 3, you can control whether to use DSP blocks or internal logic on DSP Builder.

However, when I asked the customer, this time, in Pattern 2, as a result of executing Analysis & Synthesis for the multiplier described in HDL, it was found that the internal logic was used without using the DSP block. .

Using a DSP block in the arithmetic processing part saves internal logic, but this time, it unexpectedly wastes the precious resource.

What kind of criteria is used in Quartus II for judgment?

I asked my senior.

Senpai: “Hmm, that’s a very good question, but it’s very difficult to answer.”

Boss: “Uh, what is it?”

Senpai: “Since there are various factors that determine whether it is a DSP block or internal logic, I can’t say it in one sentence.”

Chief: "Is that so?"

Senpai: I used to have the same doubts and tried various things, but it seems that even if the HDL description is the same, the synthesis result will change depending on the constraints, target device, peripheral circuit structure, and resource usage. It's like coming

For example, if you change the target device for this self-made multiplier and perform Analysis & Synthesis..."

Seniors: “See, the design is the same, but one uses DSP block resources and the other does not.”

Boss: "Huh~. It's really a 'Bimyo relationship', isn't it?"

Senpai: "Quartus II selects resources to optimize timing and area in the logic synthesis and fitting phases."

Head "Seriously... I'm in trouble. I can't answer the customer..."

Senpai: But there is a way to “prioritize” which one to use!

Boss: “Oh! Is there such a setting!!”

Senpai: “Actually, there are two of them~”

Head "Yeah! Two!"

Senpai: “There are four ways to set the settings.”

1. Describe the settings that apply to the entire circuit in a .tcl or .qsf file.

2. Describe settings to be applied to individual instances in a .tcl or .qsf file.

3. Quartus II GUI-based settings that apply to the entire circuit

4. Quartus II GUI-based configuration for individual instances

Senpai: First of all, for method 1, when you open a .qsf file or .tcl file, the default is "AUTO", so change the relevant part as follows."

set_global_assignment -name DSP_BLOCK_BALANCING "DSP BLOCKS"

Senpai ``In method 2, write the following in the same file.''

set_instance_assignment -name DSP_BLOCK_BALANCING "DSP BLOCKS" -to *****

Chief "Houhou"

Senior: "Write the instance name to be set in "*****" in the part after "-to" at the end of this description."

Boss: "I see. Then how can I set 3 and 4 in Quartus II?"

Senior: "I'll explain now."

3. Set the entire circuit using Quartus II

Senior: "Pull down and select Assignments > Settings > Analysis & Synthesis Settings > More Settings > DSP Block Balancing"

4. Set Individually Using Quartus II

Senpai: "Go to Assignments > Assignment Editor, pull down Assignment Name, select "DSP Block Balancing", and select the value you want to set."

Boss: “Oh, I see! Setting up in Quartus II is easy!”

Senpai: "Yes! If you use these setting methods to set the DSP block to use and compile..."

Head "Oh! It's reflected properly"

Senpai: “That was good.”

Boss: “Good!”

Senior: “Then, from now on, please study more about FPGA technology and support me next time.”

Boss: “Yes! I will do my best.”

Thus the foreman was able to answer a rather complicated question.

He was determined to continue to pursue technology and provide high-quality support to difficult questions, rather than giving "blind" answers.