Hello, I'm Mass Man.
To implement a clock function as part of new employee training, titled "mass man's FPGA board production"
I will serialize the blushing episode when I designed the FPGA board!
Please warmly watch over the "failures that newcomers make" (laughs).
Compensation for exceeding the absolute maximum rated voltage...
Tot's FPGA, a rookie sync, suddenly stopped working one day.
Three people in sync staring at the FPGA that has stopped moving in a daze...
(Here's a picture of the broken FPGA)
The cause was that a voltage value (5.5 V) exceeding the absolute maximum rated voltage value (4.2 V) was applied to the FPGA.
Totto: "Why was it working normally until just now!?"
Senior employee: "For example, if a car with a maximum speed of 120 km/h continues to run at 200 km/h, the engine will break.
It's the same with FPGAs, if they continue to operate beyond the absolute maximum rated voltage they will break. ”
Absolute Maximum Ratings
The maximum values of power supply voltage and input signal voltage are specified for FPGA (Table1-1).
Absolute maximum ratings are defined values that limit the device to withstand destruction.
Exceeding the absolute maximum ratings may cause fatal damage to the device.
This value varies by device family.
The device used by Masuotoko is Cyclone® IV E.
The output signal voltage of the oscillator was specified as 5.5 V, and a 5.5 V clock signal was input to the FPGA.
In fact, he used the same oscillator as Tot, and he was in danger of damaging his FPGA as well! !
About Recommended Operating Conditions
Recommended values for power supply voltage and input signal voltage are specified for FPGA (Table 1-3).
When designing a power supply, Masuoto checked Table 1-3.
I designed the power supply voltage to the FPGA to be the recommended value (Typ).
However, I neglected to check the input signal voltage to the FPGA and ended up purchasing a 5.5 V oscillator...
overshoot
After the FPGA was damaged, the output signal voltage was changed to an oscillator with 3.3 V specifications.
This time, I observed the clock signal with an oscilloscope to see if it satisfies the recommended input signal voltage (3.6 V).
The image below is the clock signal observed by applying a probe to the FPGA input terminal (Fig. 1).
As a result of observation, overshoot occurred.
The overshoot portion (overlapping noise and signal reflections) exceeded the absolute maximum rating of 3.6 V.
Masuo couldn't come up with a solution other than changing the oscillator.
I discussed this fact with a senior employee.
Mass man "The overshoot exceeded the absolute maximum rating. What should I do?"
Senior employee: “It would be nice to install a damping resistor.”
(Continue…)
what i learned
・ Never exceed the absolute maximum ratings, as doing so will severely damage the FPGA.
・ Design the FPGA board so that the voltage value of the recommended operating conditions is met.
In fact, it was already too late, and after this, I realized that Mass Man's FPGA device had been seriously damaged.