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現在2235件がヒットしています。check
Nice to meet you! It's "Poki".
I will be posting articles for the next year.
I will do my best to write articles that will help you understand.
Since I had experience with the C language, the Verilog HDL description style was easy to understand.
Since the processing of a large-scale logic circuit can be described in a program, it can be designed much easier than describing it in a circuit diagram!
This circuit uses a counter (counter:u00) and a decoder (segment:u01).
Modules called counter and segment are created, and they are called and connected in the upper layer file.
Since Quartus ® II can perform logic check function and logic synthesis, when I tried logic synthesis using Quartus ® II,
4-bit counter is logic synthesis. . . I made it!
The next 7-bit segment is logic synthesis. . . I can't!
The following Error occurred and stopped at the logic check before logic synthesis.
Error (10137): Verilog HDL Procedural Assignment error at segment.v:object "out" on left-hand side of assignment must have a variable data type
Apparently the output out of the segment module seems to be the cause.
I would like to know more. . .
At that time, my senior said something.
Seniors "How about looking at Help?"
yeah? Help? Is there such a convenient thing! ?
All you have to do is highlight the Error you want to know more about and press the F1 key!
By pressing the F1 key (You can also do the same by right-clicking and clicking Help.)
You can see the explanation of the error content in the Quartus ® II Help.
Then, the following explanation came out this time.
|
ID:10137 Verilog HDL Procedural Assignment error at <location>: object "<name>" on left-hand side of assignment must have a variable data type CAUSE: In a procedural assignment at the specified location in a Verilog Design File (.v), you assigned a value to the specified object, which was declared with a net data type (wire, wand, and so on) rather than with a variable data type (reg, integer, and so on). In Verilog HDL, you must use continuous assignments when targeting nets, and procedural assignments when targeting variables.
ACTION: Declare the specified object with a variable data type, if that is appropriate, or use a continuous assignment to assign a value to the object. ～～～～～～～～～～～～ (summary) Cause: Declaring something of a net type (wire, wand, etc.) with a variable type (reg, integer, etc.). In Verilog HDL, if the target is a net type, it must be used in a continuous assignment statement, and if it is a variable type, it must be used in a procedural assignment statement.
Workaround: Define the target of the error with a variable type, or describe the variable type defined with a procedure assignment statement. |
Change net type to variable type?
If we take another look at the segment module here,
You are using the output out in the always statement!
Since the output out is declared with wire, it cannot be used in the always statement.
I changed wire to reg as shown in Figure 3 to use it in the always statement, and I was able to successfully perform logic synthesis.
As a supplement, the data types that can be used in each statement are as follows.
continuous assignment statement assign statement: net type ( wire, wand )
procedure assignment statement (continuous assignment) always statement: variable type ( reg , integer )
By the way, my past seniors had the same problem.
After that, I created the upper layer and successfully created the circuit as shown in Figure 1 with the RTL Viewer.
I hate errors, but it's nice to know the cause.
If you are in trouble, please try "highlight (click) on Error and press F1 key" ♪
You may discover something new!
[This time's point! ]
Highlight Error and press F1 key ⇒ Go to Quartus® II Help to check details.