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Hello, I'm Mass Man.
This time, I will talk about when I stumbled on Verilog HDL syntax.

In the example sentences that came out during the training, there are two ways to describe the value assignment, and I got confused.

         "a = b"

         " a <= b "


Both mean "assign b to a".

If you look up what the difference is in the literature,

● Blocking assignment (=): Executed in order from the top within a sequential block


● Non-blocking assignment (<=): Within a sequential block, assignment can be made regardless of the order in which statements are written.

is explained.

A sequential block is the part enclosed by begin and end of the always statement.

 

I wondered, "What is the difference between the circuits that are actually synthesized?"

When I check the result with RTL Viewer,

Blocking assignment generated various circuits depending on the order of description.

The same circuit was generated regardless of the order of non-blocking assignments.

For blocking assignment (=)

always @ (posedge clk)

begin

dadb = da & db;

dcdd = dc&dd;

 dout = dadb & dcdd;

end

end module

always @ (posedge clk)

begin

dcdd = dc&dd;

 dout = dadb & dcdd;

dadb = da & db;

end

end module

 

always @ (posedge clk)

begin

 dout = dadb & dcdd;

dadb = da & db;

dcdd = dc&dd;

end

end module

 

For non-blocking assignment (<=)

always @ (posedge clk)

begin

dadb <= da & db;

dcdd <= dc & dd;

dout <= dadb & dcdd;

end

end module


always @ (posedge clk)

begin

dcdd <= dc & dd;

dout <= dadb & dcdd;

dadb <= da & db;

end

end module


always @ (posedge clk)

begin

dout <= dadb & dcdd;

dadb <= da & db;

dcdd <= dc & dd;

end

end module

what i learned

If you describe a blocking assignment in an always statement, a circuit that depends on the execution order will be generated.

 

 

If you look closely at the example sentences, the assign statement is written with blocking assignment (=), and the always statement is written with non-blocking assignment (<=).

I wrote a blocking assignment inside an always statement that created an unintended circuit and made me blush.