"IOH" why minus? , "IOL" why plus?

I was told by a senior that from the FPGA side, the difference is whether the current flows in or out.

I wondered what it means to have current coming in even though it is output current.

My head was like this.

This question was easy to answer when we considered CMOS circuits in FPGAs.

Below is a CMOS circuit for part of the IOE's output buffer.

As shown in Figure 1, the current did not flow in the same direction when the voltage was high and when the voltage was low.

I thought that electricity has a lot to do with it, and I thought in my heart that I was one step closer to handling FPGAs safely.

Tott's IOE adventure continues next time...

Summary of this time

When the output voltage is high, the current flows from the FPGA side (out of the FPGA)

↓
 
The sign of "IOH" is minus


When the output voltage is low, the current flows to the FPGA side (enters the FPGA)

↓

The sign of "IO L" is plus

Back to the previous part...