Power On Reset

A POR circuit is a circuit that keeps the entire device in reset until each supply voltage level stabilizes.

The power supplies being monitored are the following three power supplies.

●VCCINT
●VCCA
-VCCIO * Only I/O banks with configuration pins and JTAG pins are monitored

Note: Different device families have different power supply voltages monitored by the POR.

In other words, when the above three power supplies (VCCIN, VCCA, VCCIO (*)) meet the power supply specifications, the POR circuit releases the reset and configuration starts.

After power-on, during POR period, the device is in reset state, as shown in the table below.

POR ends when each power supply voltage reaches the specified value, and configuration starts by releasing nSTATUS.

If you want to start configuration after a certain amount of time has passed after the power supply stabilizes (after POR ends), you can manually set nCONFIG to Low and then set nCONFIG to High when you want to start configuration. is.

We received the following questions from our customers.

Customer: "There is a device that starts working faster than the FPGA after powering on the board. Since it is connected with the FPGA on the board, could you tell me the state of the pins of the FPGA?"

Come to think of it, I didn't know what the state of each pin of the FPGA was before configuration.

If the configuration is not completed, each pin will be in a state where it is not decided whether it is an input pin or an output pin.

Will all pins be in the same state?

When I checked the I/O status in each phase in the Cyclone® IV handbook, I found the following description.

(Details in the handbook are here ⇒ Configuration -> Configuration -> Reset)

The I/O pins are tri-stated until the device enters user mode.

The user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are always enabled (after POR) before and during configuration.

User I/Os and Dual-Purpose I/Os (dual-purpose pins) must be tri-stated after POR until configuration is complete, and the device's internal Weak Pull-Up resistors must be enabled. I understand.

The resistance value of the I/O pull-up resistors present inside the device is specified in the datasheet and depends on the voltage level of VCCIO.

(Operating Condition -> DC Characteristics -> Internal Weak Pull-Up and Weak Pull-Down Resistor)

Power supply swings seem to cause POR to go wrong, resulting in configuration failures.

If the configuration fails, it seems that only the part related to the configuration will be analyzed, but I would like to check the voltage when the power is turned on.

Initialize

Next, what kind of initialization is performed in the initialization?

As the name suggests, it initializes the device according to the logic state so that the designed logic can start operating.

Inside the device are the following and these primitives are set to the initial state of the design:

● LUT (lookup table)
● Register
●I/O
●Memory block
● Multiplier block

Summary

I understand the difference between POR and Initialize.

POR: When the power is turned on, the entire device is reset until the power supply voltage reaches the specified value.
●Initialize・・・Sets initial values to registers, memory, etc. inside the FPGA.

As the customer asked, there shouldn't be a single FPGA on the board... So, the state of user I/O and dual-purpose pins when the FPGA is not in user mode was investigated, but the configuration How can a configuration pin act as a configuration pin and when is the configuration mode known?

We will investigate the next configuration sequence.

That was the difference between POR and Initialize! I said "configuration" in one word, but it's really deep...