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Narrow down by specifying conditions
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Hello, I'm Mass Man.
Starting this week, I will be writing a series on “timing analysis”. The most difficult part of the new employee training was the lecture on timing analysis. Through this column, I would like to summarize the lecture materials and notes on timing analysis and introduce the points where I stumbled.
Today about the SDC command. Here is an example of an SDC description for TimeQuest.
There are various SDC descriptions, but in this column, I would like to introduce the SDC descriptions picked up in new employee training.
clock constraint
table 1. List of SDC commands for clock constraints.
|
command |
content |
|---|---|
| create_clock | Defines the clock frequency supplied by the clock pin. |
| create_generated_clock | Defines the clock frequency supplied by the internal logic/PLL. |
| derive_pll_clocks | Defines the clock frequency supplied by the internal PLL. A convenience command that allows you to constrain all outputs of the PLL. |
| set_clock_uncertainty | Defines the clock rise/fall time variation. The user himself can set constraints according to the board. |
| derive_clock_uncertainty | Defines the clock rise/fall time variation. Variation model prepared by Altera. |
| set_clock_latency | Define clock delay time between external device and FPGA. |
Figure 1 is an image of how each command limits the clock.
Figure 1. Image of clock constraints
I/O constraints
Table 2. List of SDC commands for I/O constraints.
|
command |
content |
|---|---|
| set_input_delay | Defines the delay time of the input signal. |
| set_output_delay | Defines the delay time of the output signal. |
| set_false_path | Exclude the specified paths from timing analysis. Used for asynchronous paths (reset/clear signals), etc. |
| set_multicycle_path | Defines analysis on any clock edge for each setup/hold. |
Figure 2 shows an image of the I/O restrictions due to each command.
Figure 2. Image of I/O constraints
In this way, the TimeQuest Timing Analyzer also considers and analyzes the relationship between the external device and the FPGA. Rather than closing on the FPGA, we are doing timing analysis for the entire board!
| Summary |
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