- Semiconductor BusinessHOME
- Products and Services of Macnica,Inc.
-
technical information
-
Events and Seminars
- Handling Manufacturer
- Support
- Inquiry
- Click here to purchase products
- Semiconductor business e-mail magazine registration
Narrow down by specifying conditions
現在2217件がヒットしています。check
In this column, we will introduce "technical information on FPGA that is surprisingly unknown, but makes a difference if you know it."
From FPGA beginners to veterans, the contents can be used widely, so please keep in touch with us until the end.
[Part 3] Verification is a combination of various methods
No single verification method can cover 100% verification.
To improve design quality, we stack various verification methods from different perspectives to make the holes as small as possible.
I compared the verification methods from different viewpoints.
Actual machine verification and logic simulation
The former is good at verifying the entire system at high speed.
The latter can be verified from the initial stage of design even with just a part of the circuit. Good at debugging.
Functional simulation and ABV (assertion-based verification)
The former is good at confirming that things are working as specified. There is a feature that makes it easy to find bugs in the latter stage of the circuit.
The latter is good at finding unexpected bugs. It has a feature that makes it easy to find bugs in the front stage of the circuit.
Code coverage and functional coverage
The former can verify the coverage rate in logic simulation. ,
The latter can verify the coverage rate with ABV (assertion-based verification).
Dynamic Verification and Static Verification
There are also two validation methods used in ABV.
In both cases, once the detection rate exceeds 95%, it will take time to further improve the detection rate. Therefore, we complement each other's methods.
For the former, a testbench is created and a logic simulation is performed.
The latter does formal verification without the need for a testbench.
In the United States, design specifications and verification specifications are created, and formal verification using UVM is used for “systematic and smart” verification. China is verifying with "human wave tactics" by many verifiers. In Japan, I have an image of verifying with "scrubbing" and "guts".