library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;

entity testbench IS
end testbench;

architecture sim of testbench is

	constant	cycle	: time	:= 20 ns;
	constant	half		: time	:= 10 ns;

	signal	CLK	:	std_logic;
	signal	CLR	:	std_logic;
	signal	PB	:	std_logic;
	signal	LED	:	std_logic_vector(3 downto 0);

	component niosv_led_c10lp 
		PORT
		(
			CLK	:	in  std_logic;
			CLR	:	in  std_logic;
			PB	:	in  std_logic;
			LED	:	out  std_logic_vector(3 downto 0)
		);
	end component;

begin

	FPGA : niosv_led_c10lp
		port map (
			CLK	=> CLK,
			CLR => CLR,
			PB	=> PB,
			LED	=> LED
			);

	CLOCK : process begin
		CLK <= '0';
		wait for half;
		CLK <= '1';
		wait for half;
	end process CLOCK;
	
	RESET : process begin
		CLR <= '1';
		wait for cycle * 10000;
		CLR <= '0';
		wait for cycle * 50000;
		CLR <= '1';
		wait;
	end process RESET;
	
	PUSH : process begin
		PB <= '1';
		wait for cycle * 80000;
		PB <= '0';
		wait for cycle * 30000;
		PB <= '1';
	end process PUSH;
		
end sim;